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Stochastic Bounds for Markov Chains on Intel Xeon Phi Coprocessor

  • Jarosław BylinaEmail author
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 10777)

Abstract

The author presents an approach to find stochastic bounds for Markov chains with the use of Intel Xeon Phi coprocessor. A known algorithm is adapted to study the potential of the MIC architecture in algorithms needing a lot of memory access and exploit it in the best way.

The paper also discusses possible sparse matrices storage schemes suitable to the investigated algorithm on Intel Xeon Phi coprocessor.

The article shows also results of the experiments with the algorithm with different compile-time and runtime parameters (like scheduling, different number of threads, threads to cores mapping).

Keywords

Intel Xeon Phi MIC architecture Markov chains Stochastic bounds Sparse matrices 

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Copyright information

© Springer International Publishing AG, part of Springer Nature 2018

Authors and Affiliations

  1. 1.Institute of MathematicsMarie Curie-Skłodowska UniversityLublinPoland

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