Symbolic Execution and Reachability Analysis Using Rewriting Modulo SMT for Spatial Concurrent Constraint Systems with Extrusion

Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 10811)

Abstract

The usual high degree of assurance in safety-critical systems is being challenged by a new incarnation of distributed systems exposed to the presence of hierarchical computation (e.g., virtualization resources such as container and virtual machine technology). This paper addresses the issue of symbolically specifying and verifying properties of distributed hierarchical systems using rewriting modulo SMT, a symbolic approach for rewriting logic that seamlessly combines rewriting modulo theories, SMT solving, and model checking. It presents a rewrite theory \(\mathcal {R}\) implementing a symbolic executable semantics of an algebraic model of spatially constrained concurrent process with extrusion. The underlying constraint system in \(\mathcal {R}\) is materialized with the help of SMT-solving technology, where the constraints are quantifier-free formulas interpreted over the Booleans and integers, and information entailment is queried via semantic inference. Symbolic rewrite steps with \(\rightarrow _\mathcal {R}\) capture all possible traces from ground instances of the source state to the ground instances of the target state. This approach, as illustrated with some examples in the paper, is well-suited for specifying and proving (or disproving) existential reachability properties of distributed hierarchical systems, such as fault-tolerance, consistency, and privacy.

Notes

Acknowledgments

The authors would like to thank C. Rueda and F. Valencia for the fruitful discussions on these ideas, and the anonymous referees for their comments that helped in improving the paper. The first author was partially supported by Colciencias’ Convocatoria 761 Jóvenes Investigadores e Innovadores 2016.

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Copyright information

© Springer International Publishing AG, part of Springer Nature 2018

Authors and Affiliations

  1. 1.Department of Electronics and Computer SciencePontificia Universidad JaverianaCaliColombia

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