Abstract
Synchronization mechanisms have been central issues in the race toward the computing units parallelization. Indeed when the number of cores increases, the applications are split into more and more software tasks, leading to the higher use of synchronization primitives to preserve the initial application services. In this context, providing efficient synchronization mechanisms turns to be essential to leverage parallelism offered by Multi-Processor Systems-on-Chip.
By using an instrumented emulation platform allowing us to extract accurate timing information, in a non-intrusive way, we led a fine analysis of the synchronization barriers of the GNU OpenMP library. This study reveals that a time expensive function was uselessly called during the barrier awakening process. We propose here a software optimization of this library that saves up to \(80\%\) of the release phase duration for a 16-core MSoCs. Moreover, being localized into the middle-ware OpenMP library, benefiting this optimization requires no specific care from the application programmer’s point of view, but a library update and can be used on every kinds of platform.
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France-Pillois, M., Martin, J., Rousseau, F. (2018). Optimization of the GNU OpenMP Synchronization Barrier in MPSoC. In: Berekovic, M., Buchty, R., Hamann, H., Koch, D., Pionteck, T. (eds) Architecture of Computing Systems – ARCS 2018. ARCS 2018. Lecture Notes in Computer Science(), vol 10793. Springer, Cham. https://doi.org/10.1007/978-3-319-77610-1_5
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DOI: https://doi.org/10.1007/978-3-319-77610-1_5
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