Abstract
Algorithms with operations on large regular data structures such as image processing can be highly accelerated when executed as hardware tasks in an FPGA fabric. The Dynamic Partial Reconfiguration (DPR) feature of new SRAM-based FPGA families allows a dynamic swapping and replacement of hardware tasks during runtime. Particularly embedded systems with processing chains that change over time or that are too large to be implemented in an FPGA fabric in parallel, benefit from DPR. In this paper we present a complete framework for hardware acceleration using DPR in the microkernel based Genode OS. This makes the DPR feature available not only for the high-performance computing field, but also for safety-critical applications. The new framework is evaluated for an exemplary imaging application running on a Xilinx Zynq-7000 SoC.
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References
Lomuscio, A., Cardarilli, G.C., Nannarelli, A., Re, M.: A hardware framework for on-chip FPGA acceleration. In: 2016 International Symposium on Integrated Circuits (ISIC), pp. 1–4, December 2016
Genode Labs: Genode OS framework. http://genode.org/. Accessed 12 October 2017
TUBS.digital: Controlling concurrent change. http://ccc-project.org/. Accessed 26 October 2017
Vipin, K., Fahmy, S.A.: A high speed open source controller for FPGA partial reconfiguration. In: 2012 International Conference on Field-Programmable Technology, pp. 61–66, December 2012
Xia, T., Prévotet, J.C., Nouvel, F.: Microkernel dedicated for dynamic partial reconfiguration on ARM-FPGA platform. ACM SIGBED Rev. 11(4), 31–36 (2015)
Xia, T., Prévotet, J.C., Nouvel, F.: Mini-nova: a lightweight ARM-based virtualization microkernel supporting dynamic partial reconfiguration. In: 2015 IEEE International Parallel and Distributed Processing Symposium Workshops, pp. 71–80, May 2015
Claus, C., Stechele, W., Herkersdorf, A.: Autovision - a run-time reconfigurable MPSoC architecture for future driver assistance systems. IT Inf. Technol. 49, 181–187 (2007)
Claus, C., Zhang, B., Stechele, W., Braun, L., Hubner, M., Becker, J.: A multi-platform controller allowing for maximum dynamic partial reconfiguration throughput. In: 2008 International Conference on Field Programmable Logic and Applications, pp. 535–538, September 2008
Hübner, M., Göhringer, D., Noguera, J., Becker, J.: Fast dynamic and partial reconfiguration data path with low hardware overhead on Xilinx FPGAs. In: IEEE International Symposium on Parallel Distributed Processing, Workshops and Ph.D. Forum (IPDPSW), pp. 1–8, April 2010
Kadi, M.A., Rudolph, P., Göhringer, D., Hübner, M.: Dynamic and partial reconfiguration of Zynq 7000 under Linux. In: International Conference on Reconfigurable Computing and FPGAs (ReConFig), pp. 1–5, December 2013
Dörflinger, A., Fiethe, B., Michalik, H., Fekete, S.P., Keldenich, P., Scheffer, C.: Resource-efficient dynamic partial reconfiguration on FPGAs for space instruments. In: 2017 NASA/ESA Conference on Adaptive Hardware and Systems (AHS), pp. 24–31, July 2017
Xilinx Inc.: Partial reconfiguration of a hardware accelerator on Zynq-7000 All programmable SoC devices, XAPP1159. v1.0 edn (2013)
Xilinx Inc.: Zynq-7000 all programmable SoC TRM, UG585. v1.11 edn (2016)
Kohn, C.: Partial reconfiguration of a hardware accelerator with Vivado design suite for Zynq-7000 AP SoC processor. Xilinx Inc. v1.1 edn (2015)
Xilinx Inc.: AXI DMA LogiCORE IP Product Guide, PG021. v7.1 edn (2017)
Xilinx Inc.: AXI Video Direct Memory Access LogiCORE IP Product Guide, PG020. v6.2 edn (2016)
Acknowledgment
This work is part of the DFG Research Group FOR 1800 “Controlling Concurrent Change”. Funding for the Institute of Computer and Network Engineering (IDA) was provided under grant number MI 1172/3-1.
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Dörflinger, A., Albers, M., Fiethe, B., Michalik, H. (2018). Hardware Acceleration in Genode OS Using Dynamic Partial Reconfiguration. In: Berekovic, M., Buchty, R., Hamann, H., Koch, D., Pionteck, T. (eds) Architecture of Computing Systems – ARCS 2018. ARCS 2018. Lecture Notes in Computer Science(), vol 10793. Springer, Cham. https://doi.org/10.1007/978-3-319-77610-1_21
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DOI: https://doi.org/10.1007/978-3-319-77610-1_21
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