Hardware Acceleration in Genode OS Using Dynamic Partial Reconfiguration

  • Alexander Dörflinger
  • Mark Albers
  • Björn Fiethe
  • Harald Michalik
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 10793)


Algorithms with operations on large regular data structures such as image processing can be highly accelerated when executed as hardware tasks in an FPGA fabric. The Dynamic Partial Reconfiguration (DPR) feature of new SRAM-based FPGA families allows a dynamic swapping and replacement of hardware tasks during runtime. Particularly embedded systems with processing chains that change over time or that are too large to be implemented in an FPGA fabric in parallel, benefit from DPR. In this paper we present a complete framework for hardware acceleration using DPR in the microkernel based Genode OS. This makes the DPR feature available not only for the high-performance computing field, but also for safety-critical applications. The new framework is evaluated for an exemplary imaging application running on a Xilinx Zynq-7000 SoC.



This work is part of the DFG Research Group FOR 1800 “Controlling Concurrent Change”. Funding for the Institute of Computer and Network Engineering (IDA) was provided under grant number MI 1172/3-1.


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Copyright information

© Springer International Publishing AG, part of Springer Nature 2018

Authors and Affiliations

  • Alexander Dörflinger
    • 1
  • Mark Albers
    • 1
  • Björn Fiethe
    • 1
  • Harald Michalik
    • 1
  1. 1.Institute of Computer and Network Engineering (IDA)TU BraunschweigBraunschweigGermany

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