HLS Enabled Partially Reconfigurable Module Implementation

  • Nicolae Bogdan Grigore
  • Charalampos Kritikakis
  • Dirk Koch
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 10793)


Making full use of the capabilities of the FPGA as an accelerator is difficult for non hardware experts, especially if partial reconfiguration is to be employed. One of the issues that arise is to physically implement modules into bounding boxes of minimum size for improving fragmentation cost and reconfiguration time. In this paper we present a method which automates the modules designing step, fulfilling module resource requirements and architectural FPGA constraints. We present a case study that shows how our automatic module implementation flow can be used to generate run-time reconfigurable bitstreams that are suited for stitching together processing pipelines directly from a Maxeler MaxJ HLS specification. This takes into consideration design alternatives, fragmentation, and routing failure mitigation strategies.



This work is kindly supported by the European Commission under the H2020 Programme with the project ECOSCALE (grant agreement 671632) and with the project Reconfigurable Tera Stream Computing, funded by the Defence Science and Technology Laboratory under grant DSTLX10000092266.


  1. 1.
    Wirbel, L.: Xilinx SDAccel (2014)Google Scholar
  2. 2.
    Stone, J.E., Gohara, D., Shi, G.: OpenCL: a parallel programming standard for heterogeneous computing systems. Comput. Sci. Eng. 12(3), 66–73 (2010)CrossRefGoogle Scholar
  3. 3.
    Sohanghpurwala, A.A., Athanas, P., Frangieh, T., Wood, A.: OpenPR: an open-source partial-reconfiguration toolkit for Xilinx FPGAs. In: 2011 IEEE International Symposium on Parallel and Distributed Processing Workshops and Ph.D. Forum (IPDPSW), pp. 228–235. IEEE (2011)Google Scholar
  4. 4.
  5. 5.
    Carver, J.M., Pittman, R.N., Forin, A.: Automatic bus macro placement for partially reconfigurable FPGA designs. In: Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, pp. 269–272. ACM (2009)Google Scholar
  6. 6.
    Vipin, K., Fahmy, S.A.: Mapping adaptive hardware systems with partial reconfiguration using CoPR for Zynq. In: 2015 NASA/ESA Conference on Adaptive Hardware and Systems (AHS), pp. 1–8. IEEE (2015)Google Scholar
  7. 7.
    Beckhoff, C., Koch, D., Torreson, J.: Automatic floorplanning and interface synthesis of island style reconfigurable systems with GoAhead. In: Kubátová, H., Hochberger, C., Daněk, M., Sick, B. (eds.) ARCS 2013. LNCS, vol. 7767, pp. 303–316. Springer, Heidelberg (2013). CrossRefGoogle Scholar
  8. 8.
    Beckhoff, C., Koch, D., Torresen, J.: GoAhead: a partial reconfiguration framework. In: IEEE 20th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), pp. 37–44. IEEE (2012)Google Scholar
  9. 9.
    Rabozzi, M., Durelli, G.C., Miele, A., Lillis, J., Santambrogio, M.D.: Floorplanning automation for partial-reconfigurable FPGAs via feasible placements generation. IEEE Trans. Very Large Scale Integr. VLSI Syst. 25(1), 151–164 (2017)CrossRefGoogle Scholar
  10. 10.
    Mao, F., Chen, Y.-C., Zhang, W., Li, H.H., He, B.: Library-based placement and routing in FPGAs with support of partial reconfiguration. ACM Trans. Des. Autom. Electron. Syst. (TODAES) 21(4), 71 (2016)Google Scholar
  11. 11.
    Otero, A., Morales-Cas, A., Portilla, J., de la Torre, E., Riesgo, T.: A modular peripheral to support self-reconfiguration in SoCs. In: 2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD), pp. 88–95. IEEE (2010)Google Scholar
  12. 12.
    Lalevee, A., Horrein, P.-H., Arzel, M., Hübner, M., Vaton, S.: AutoReloc: automated design flow for bitstream relocation on Xilinx FPGAs. In: 2016 Euromicro Conference on Digital System Design (DSD), pp. 14–21. IEEE (2016)Google Scholar
  13. 13.
    Ferrandi, F., Novati, M., Morandi, M., Santambrogio, M.D., Sciuto, D.: Dynamic reconfiguration: core relocation via partial bitstreams filtering with minimal overhead. In: International Symposium on System-on-Chip, pp. 1–4. IEEE (2006)Google Scholar
  14. 14.
    Kalte, H., Lee, G., Porrmann, M., Ruckert, U.: Replica: a bitstream manipulation filter for module relocation in partial reconfigurable systems. In: Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium, pp. 8–pp. IEEE (2005)Google Scholar
  15. 15.
    DeHon, A.: Balancing interconnect and computation in a reconfigurable computing array (or, why you don’t really want 100% LUT utilization). In: Proceedings of the 1999 ACM/SIGDA Seventh International Symposium on Field Programmable Gate Arrays, pp. 69–78. ACM (1999)Google Scholar
  16. 16.
    Maxeler Technologies: Multiscale dataflow programing (2014)Google Scholar
  17. 17.
    Maxeler App Gallery (2017).

Copyright information

© Springer International Publishing AG, part of Springer Nature 2018

Authors and Affiliations

  • Nicolae Bogdan Grigore
    • 1
  • Charalampos Kritikakis
    • 1
  • Dirk Koch
    • 1
  1. 1.The University of ManchesterManchesterUK

Personalised recommendations