Improving the Performance of STT-MRAM LLC Through Enhanced Cache Replacement Policy

  • Pierre-Yves Péneau
  • David Novo
  • Florent Bruguier
  • Lionel Torres
  • Gilles Sassatelli
  • Abdoulaye Gamatié
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 10793)


Modern architectures adopt large on-chip cache memory hierarchies with more than two levels. While this improves performance, it has a certain cost in area and power consumption. In this paper, we consider an emerging non volatile memory technology, namely the Spin-Transfer Torque Magnetic RAM (STT-MRAM), with a powerful cache replacement policy in order to design an efficient STT-MRAM Last-Level Cache (LLC) in terms of performance. Well-known benefits of STT-MRAM are their near-zero static power and high density compared to volatile memories. Nonetheless, their high write latency may be detrimental to system performance. In order to mitigate this issue, we combine STT-MRAM with a recent cache The benefit of this combination is evaluated through experiments on SPEC CPU2006 benchmark suite, showing performance improvements of up to 10% compared to SRAM cache with LRU on a single core system.



This work has been funded by the French ANR agency under the grant ANR-15-CE25-0007-01, within the framework of the CONTINUUM project.


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Copyright information

© Springer International Publishing AG, part of Springer Nature 2018

Authors and Affiliations

  • Pierre-Yves Péneau
    • 1
  • David Novo
    • 1
  • Florent Bruguier
    • 1
  • Lionel Torres
    • 1
  • Gilles Sassatelli
    • 1
  • Abdoulaye Gamatié
    • 1
  1. 1.LIRMMCNRS and University of MontpellierMontpellierFrance

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