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Delta-Sigma Modulators

  • Qiyuan Liu
  • Alexander Edward
  • Carlos Briseno-Vidrios
  • Jose Silva-Martinez
Chapter

Abstract

This chapter provides a general overview on the discrete-time ΔΣMs (DTΣΔΣMs) and continuous-time ΔΣMs (CTΔΣMs). An introduction on two different topologies of implementing high-order CTΔΣMs, single-loop and MASH, is presented. The benefits of employing a MASH topology for CT-ΔΣMs are also discussed in this chapter.

References

  1. 1.
    H. Inose, Y. Yasuda, J. Murakami, A telemetering system by code modulation – Δ − Σ modulation. IRE Trans. Space Electron. Telem. 8(3), 204–209 (1962)CrossRefGoogle Scholar
  2. 2.
    R. Jiang, T.S. Fiez, A 14-bit ΔΣ ADC with 8 × OSR and 4-MHz conversion bandwidth in a 0.18-μm CMOS process. IEEE J. Solid State Circuits 39(1), 63–74 (2004)Google Scholar
  3. 3.
    Y. Dong, J. Zhao, W. Yang, T. Caldwell, H. Shibata, R. Schreier, Q. Meng, J. Silva, D. Paterson, J. Gealow, A 930mW 69dB-DR 465MHz-BW CT 1-2 MASH ADC in 28nm CMOS, in IEEE Int. Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, San Francisco (2016), pp. 278–279Google Scholar
  4. 4.
    B.R. Carlton, H. Lakdawala, E. Alpman, J. Rizk, Y.W. Li, B. Perez-Esparza, V. Rivera, C.F. Nieva, E. Gordon, P. Hackney, C.-H. Jan, I.A. Young, K. Soumyanath, A 32nm, 1.05V, BIST enabled, 10–40MHz, 11-9 bit, 0.13mm2 digitized integrator MASH ΔΣ ADC, in IEEE Int. Symp. VLSI Circuits (VLSI) Dig. Tech. Papers, Kyoto (2011), pp. 36–37Google Scholar
  5. 5.
    Y. Matsuya, K. Uchimura, A. Iwata, T. Kobayashi, M. Ishikawa, T. Yoshitome, A 16-bit oversampling A-to-D conversion technology using triple-integration noise shaping. IEEE J. Solid State Circuits 22(6), 921–929 (1987)CrossRefGoogle Scholar
  6. 6.
    R. Schreier, G. Temes, Understanding Delta-Sigma Data Converters (Willey/IEEE, New York, 2004)CrossRefGoogle Scholar
  7. 7.
    T.C. Leslie, B. Singh, An improved sigma-delta modulator architecture, in IEEE Int. Symp. Circuits and Systems, New Orleans (1990), pp. 372–375Google Scholar
  8. 8.
    A. Gharbiya, D.A. Johns, A 12-bit 3.125 MHz bandwidth 0-3 MASH delta-sigma modulator. IEEE J. Solid State Circuits 44(7), 2010–2018 (2009)Google Scholar
  9. 9.
    N. Maghari, S. Kwon, U.-K. Moon, 74 dB SNDR multi-loop sturdy-MASH delta-sigma modulator using 35 dB open-loop opamp gain. IEEE J. Solid State Circuits 44(8), 2212–2221 (2009)CrossRefGoogle Scholar

Copyright information

© Springer International Publishing AG, part of Springer Nature 2018

Authors and Affiliations

  • Qiyuan Liu
    • 1
  • Alexander Edward
    • 2
  • Carlos Briseno-Vidrios
    • 3
  • Jose Silva-Martinez
    • 4
  1. 1.Qualcomm IncorporatedTempeUSA
  2. 2.Intel CorporationHillsboroUSA
  3. 3.Silicon Laboratories IncorporatedAustinUSA
  4. 4.Department of Electrical and Computer EngineeringTexas A&M UniversityCollege StationUSA

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