Abstract
This chapter introduces the motivation of employing MASH continuous-time Delta-Sigma modulators (CTΔΣMs) for long-term-evolution advanced (LTE-A), WiFi and next generation wide-bandwidth telecommunication standards. Compared with high-order single-loop implementations, MASH CTΔΣMs show superior stability and overload recovery capability. Therefore, MASH modulators tolerate more out-of-band noise and show a promising potential for wide-bandwidth and low-power capability. Nevertheless, the noise leakage due to the poor matching between analog and digital transfer function and the nonideal inter-stage interfacing are the main limitations of the MASH CTΔΣM topology. The work focuses on the analysis and design of MASH CTΔΣMs. System- and circuit-level design techniques are proposed to enable MASH CTΔΣMs to its full potential. An overview of the scope and organization of the book is also provided in this chapter.
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References
N. Klemmer, S. Akhtar, V. Srinivasan, P. Litmanen, H. Arora, S. Uppathil, S. Kaylor, A. Akour, V. Wang, M. Mares, F. Dulger, A. Frank, D. Ghosh, S. Madhavapeddi, H. Safiri, J. Mehta, A. Jain, H. Choo, E. Zhang, C. Sestok, C. Fernando, K. Rajagopal, S. Ramakhrisnan, V. Sinari, V. Baireddy, A 45nm CMOS RF-to-bits LTE/WCDMA FDD/TDD 2x2 MIMO base-station transceiver SoC with 200 MHz RF bandwidth, in IEEE Int. Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, San Francisco (2016), pp. 164–165
J. Wannstrom, Long-term-evolution advanced (LTE-A) [Online] (2013). Available: http://www.3gpp.org/technologies/keywords-acronyms/97-lte-advanced
C. Briseno-Vidrios, A. Edward, A. Shafik, S. Palermo, J. Silva-Martinez, A 75-MHz continuous-time sigma-delta modulator employing a broadband low-power highly efficient common-gate summing stage. IEEE J. Solid State Circuits 52(3), 657–668 (2017)
A. Edward, Q. Liu, C. Briseno-Vidrios, M. Kinyua, E.G. Soenen, A.I. Karsilayan, J. Silva-Martinez, A 43-mW MASH 2-2 CT ΣΔ modulator attaining 74.4/75.8/76.8 dB of SNDR/SNR/DR and 50 MHz of BW in 40-nm CMOS. IEEE J. Solid State Circuits 52(2), 448–459 (2017)
C. Briseno-Vidrios, A. Edward, N. Rashidi, J. Silva-Martinez, A 4 bit continuous-time ΣΔ modulator with fully digital quantization noise reduction algorithm employing a 7 bit quantizer. IEEE J. Solid State Circuits 51(6), 1398–1409 (2016)
Q. Liu, A. Edward, D. Zhou, J. Silva-Martinez, A continuous-time MASH 1-1-1 delta-sigma modulator with FIR DAC and encoder-embedded loop-unrolling quantizer in 40-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 99, 1–12 (2017)
B. Murmann, ADC performance survey [Online] (2010–2017). Available http://www.stanford.edu/~murmann/adcsurvey.html
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Liu, Q., Edward, A., Briseno-Vidrios, C., Silva-Martinez, J. (2018). Introduction. In: Design Techniques for Mash Continuous-Time Delta-Sigma Modulators. Springer, Cham. https://doi.org/10.1007/978-3-319-77225-7_1
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DOI: https://doi.org/10.1007/978-3-319-77225-7_1
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Online ISBN: 978-3-319-77225-7
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