Pathfinding and Co-design
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In this chapter, we will learn about die-package-board pathfinding and co-design. We will also learn about basics of device floorplanning and co-design. A number of industry-based examples are provided to demonstrate the integration process. Co-design and pathfinding methodologies presented in this chapter build the foundation of 2.5D/3D heterogeneous integration.
KeywordsSilicon interposer 2.5D/3D Heterogeneous Integration Interconnect Packaging PCB System design Pathfinding Methodology Optimization Wide I/O HBM Partition Logic Memory I/O buffer cell Flip chip Die System in package SIP BGA MCM 3D IC Device Substrate Mixed-signals
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- 2.Yazdani F, Park J (2014) Pathfinding methodology for optimal design and integration of 2.5D/3D interconnects. In: Proceedings of the 64th IEEE electronic components and technology conference, Orlando, Florida, 26–30 May 2014Google Scholar