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Blocked All-Pairs Shortest Paths Algorithm on Intel Xeon Phi KNL Processor: A Case Study

  • Enzo Rucci
  • Armando De Giusti
  • Marcelo Naiouf
Conference paper
Part of the Communications in Computer and Information Science book series (CCIS, volume 790)

Abstract

Manycores are consolidating in HPC community as a way of improving performance while keeping power efficiency. Knights Landing is the recently released second generation of Intel Xeon Phi architecture. While optimizing applications on CPUs, GPUs and first Xeon Phi’s has been largely studied in the last years, the new features in Knights Landing processors require the revision of programming and optimization techniques for these devices. In this work, we selected the Floyd-Warshall algorithm as a representative case study of graph and memory-bound applications. Starting from the default serial version, we show how data, thread and compiler level optimizations help the parallel implementation to reach 338 GFLOPS.

Keywords

Xeon Phi Knights Landing Floyd-Warshall 

Notes

Acknowledgments

The authors thank the ArTeCS Group from Universidad Complutense de Madrid for letting use their Xeon Phi KNL system.

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Copyright information

© Springer International Publishing AG, part of Springer Nature 2018

Authors and Affiliations

  • Enzo Rucci
    • 1
  • Armando De Giusti
    • 1
  • Marcelo Naiouf
    • 2
  1. 1.III-LIDI, CONICET, Facultad de InformáticaUniversidad Nacional de La PlataLa PlataArgentina
  2. 2.III-LIDI, Facultad de InformáticaUniversidad Nacional de La PlataLa PlataArgentina

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