Advertisement

Analysis of RAPL Energy Prediction Accuracy in a Matrix Multiplication Application on Shared Memory

  • Juan Manuel Paniego
  • Silvana Gallo
  • Martín Pi Puig
  • Franco Chichizola
  • Laura De Giusti
  • Javier Balladini
Conference paper
Part of the Communications in Computer and Information Science book series (CCIS, volume 790)

Abstract

In recent years, energy consumption has emerged as one of the biggest issues in the development of HPC applications. The traditional approach of parallel and distributed computing has changed its perspective from looking for greater computational efficiency to an approach that balances performance with energy consumption. As a consequence, different metrics and measurement mechanisms have been implemented to achieve this balance. The objective of this article focuses on monitoring and analyzing energy consumption for a given application through physical measurements and a software interface based on hardware counters. A comparison of the energy values gathered by Intel RAPL versus physical measurements obtained through the processor power source is presented. These measurements are applied during the execution of a classic matrix multiplication application. Our results show that, for the application being considered, the average power required by the processor has an error of up to 22% versus the values predicted by RAPL.

Keywords

Energy consumption Prediction Power Hardware counters RAPL Perf 

References

  1. 1.
    AMD, AMD Family 15th Processor BIOS and Kernel Developer Guide (2011)Google Scholar
  2. 2.
    Balladini, J., Muresano, R., Suppi, R., Rexachs, D., Luque, E.: Methodology for predicting the energy consumption of SPMD application on virtualized environments. J. Comput. Sci. Technol. 13(3), 130–136 (2013)Google Scholar
  3. 3.
    Balladini, J., Rucci, E., De Giusti, A., Naiouf, M., Suppi, R., Rexachs, D., Luque, E.: Power characterisation of shared-memory HPC systems. In: XVIII Argentine Congress of Computer Science Selected Papers. Computer Science & Technology Series, pp. 53–65 (2013)Google Scholar
  4. 4.
    Bircher, W., John, L.: Complete system power estimation using processor performance events. IEEE Trans. Comp. 61(4), 563–577 (2012)MathSciNetCrossRefzbMATHGoogle Scholar
  5. 5.
    Lively, C., Wu, X., Taylor, V., Moore, S., Chang, H., Su, C., Cameron, K.: Power-aware predictive models of hybrid (MPI/OpenMP) scientific applications on multicore system. Comput. Sci. Res. Dev. 27(4), 245–253 (2012)CrossRefGoogle Scholar
  6. 6.
    Chen, X., Xu, C., Dick, R., Mao, Z.: Performance and power modeling in a multi-programmed multi-core environment. In: 2010 47th ACM/IEEE Design Automation Conference (DAC 2010), pp. 813–818 (2010)Google Scholar
  7. 7.
    Contreras, G., Martonosi, M.: Power prediction for Intel XScale processors using performance monitoring unit events. In: Proceedings of the 2005 International Symposium on Low Power Electronic and Design, ISLPED 2005, pp. 221–226 (2005)Google Scholar
  8. 8.
    David, H., Gorbatov, E.: RAPL: memory power estimation and capping. In: 2010 ACM/IEEE International Symposium on Low-Power Electronics and Design (ISLPED), pp. 189–194 (2010)Google Scholar
  9. 9.
    Desrochers, S., Paradis, C., Weaver, V.M.: A validation of DRAM RAPL power measurements. In: Second International Symposium on Memory Systems, pp. 445–470 (2016)Google Scholar
  10. 10.
    Diouri, M.E.M., Dolz, M.: Assessing power monitoring approaches for energy and power analysis of computers. Sustain. Comput. Inf. Syst. 4(2), 68–82 (2014)Google Scholar
  11. 11.
    Ge, R., Feng, X., Song, S., Chang, H.C., Li, D., Cameron, K.W.: PowerPack: energy profiling and analysis of high-performance systems and applications. IEEE Trans. Parallel Distrib. Syst. 21(5), 658–671 (2010)CrossRefGoogle Scholar
  12. 12.
    Hackenberg, D., Ilsche, I., Schone, R., Molka, D., Schmidt, M., Nagel, W.E.: Power measurement techniques on standard compute nodes: a quantitative comparison. In: IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS) (2013)Google Scholar
  13. 13.
    Hahnel, M., Dobel, B., Volp, M., Hartigl, H.: Measuring energy consumption for short code paths using RAPL. ACM SIGMETRICS Perform. Eval. Rev. 40, 13–17 (2012). Technische Universität DresdenCrossRefGoogle Scholar
  14. 14.
    Intel Architecture Software Developer’s Manual, volume 3: System Programming Guide (2009)Google Scholar
  15. 15.
    Isci, C., Martonosi, M.: Runtime power monitoring in high-end processors: methodology and empirical data. In: 36th IEEE/ACM International Symposium on Microarchitecture, p. 93 (2003)Google Scholar
  16. 16.
    Khan, K.N., Ou, Z., Hirki, M., Nurminen, J.K., Niemi, T.: How much power does your server consume? Estimating wall socket power using RAPL measurements. Comput. Sci. Res. Dev. 31, 207–214 (2016)CrossRefGoogle Scholar
  17. 17.
    Lim, M., Porterfield, A., Fowler, R.: SoftPower: finegrain power estimations using performance counters. In: Proceedings of the 19th ACM International Symposium on High Performance Distributed Computing (HPDC 2010), pp. 308–311 (2010)Google Scholar
  18. 18.
    Lively, C., Taylor, V., Wu, X., Chang, H., Su, C., Cameron, K., Moore, S., Terpstra, D.: E-AMOM: an energy-aware modeling and optimization methodology for scientific applications on multicore systems. Comput. Sci. Res. Dev. 29(3–4), 197–210 (2014)CrossRefGoogle Scholar
  19. 19.
    Mucci, P., Browne, S., Deane, C., Ho, G.: PAPI: a portable interface to hardware performance counters. In: Proceedings of the Department of Defense HPCMP Users Group Conference, pp. 7–10 (1999)Google Scholar
  20. 20.
    Nagasaka, H., Maruyama, N., Nukada, A., Endo, T., Matsuoka, S.: Statistical power modeling of GPU kernels using performance counters. In: International Green Computing Conference, pp. 115–122 (2010)Google Scholar
  21. 21.
    Picariello, F., Rapuano, S., Villano, U.: Evaluation of power consumption of workstation computers using benchmarking. In: Proceedings 12th IMEKO TC10 Workshop on Technical Diagnostics: New Perspective in Measurements, Tools and Techniques for Industrial Applications, University of Sannio, Italy, pp. 242–247 (2013)Google Scholar
  22. 22.
    Singh, K., Bhadhauria, M., McKee, S.A.: Real time power estimation and thread scheduling via performance counters. In: Workshop on Design, Architecture and Simulation of Chip Multi-Processors, vol. 37(2), pp. 46–55, May 2009Google Scholar
  23. 23.
    Song, S., Su, C., Rountree, B., Cameron, K.: A simplified and accurate model of power-performance efficiency on emergent GPU architectures. In: 2013 International Symposium on Parallel & Distributed Processing, IPDPS 2013, pp. 673–686 (2013)Google Scholar
  24. 24.
    Tsafack Chetsa, G.L., Lefevre, L., Pierson, J.M., Stolf, P., Da Costa, G.: Exploiting performance counters to predict and improve energy performance of HPC systems. Future Gener. Comput. Syst. 36, 287–298 (2014)CrossRefGoogle Scholar

Copyright information

© Springer International Publishing AG, part of Springer Nature 2018

Authors and Affiliations

  • Juan Manuel Paniego
    • 1
  • Silvana Gallo
    • 1
    • 3
  • Martín Pi Puig
    • 1
  • Franco Chichizola
    • 1
  • Laura De Giusti
    • 1
  • Javier Balladini
    • 2
  1. 1.Instituto de Investigación en Informática LIDI (III-LIDI), Facultad de InformáticaUniversidad Nacional de La PlataLa PlataArgentina
  2. 2.Departamento de Ingeniería de Computadoras, Facultad de InformáticaUniversidad Nacional del ComahueNeuquénArgentina
  3. 3.CONICET, Facultad de InformáticaUniversidad Nacional de La PlataLa PlataArgentina

Personalised recommendations