Advertisement

Substrate Coupling Analysis and Evaluation of Protection Strategies

  • Pietro Buccella
  • Camillo Stefanucci
  • Maher Kayal
  • Jean-Michel Sallese
Chapter
Part of the Analog Circuits and Signal Processing book series (ACSP)

Abstract

In this chapter, the EPFL substrate model is used to analyze substrate parasitic couplings in high-voltage ICs. With this analysis, circuit performance under substrate current is quickly estimated with SPICE simulations enabling the design of appropriate isolation structures and the optimization of the layout floor plan accordingly. Solutions that most effectively reduce such couplings in a chip are based on the physical separation and the placement of guard rings acting as protections. Such protections are placed between the parasitic injector device and the victims, which are often sensitive analog circuits. A systematic approach to characterize key electrical parameters of guard rings acting as protection is also proposed in this chapter. Finally, a comparative study showing the basic design, the working principle, and the advantages and disadvantages of various protection strategies is presented and compared with already published results.

References

  1. 1.
    W. Horn, H. Zitta, A robust smart power bandgap reference circuit for use in an automotive environment. IEEE J. Solid State Circuits 37(7), 949–952 (2002)CrossRefGoogle Scholar
  2. 2.
    M. Schrems, M. Knaipp, H. Enichlmair, V. Vescoli, R. Minixhofer, E. Seebacher, F. Leisenberger, E. Wachmann, G. Schatzberger, H. Gensinger, Scalable high voltage CMOS technology for smart power and sensor applications. e & i Elektrotechnik und Informationstechnik 125(4), 109–117 (2008)Google Scholar
  3. 3.
    R.J. Widlar, Controlling substrate currents in junction-isolated ICs. IEEE J. Solid State Circuits 26(8), 1090–1097 (1991)CrossRefGoogle Scholar
  4. 4.
    A. Hastings, The Art of Analog Layout (Prentice Hall, Lebanon, 2005)Google Scholar
  5. 5.
    International Organization for Standardization, ISO 7637-2 Road vehicles electrical disturbances from conduction and coupling Part 2: electrical transient conduction along supply lines only (2011)Google Scholar
  6. 6.
    S.H. Voldman, Latchup (Wiley, New York, 2008)Google Scholar
  7. 7.
    O. Gonnard, G. Charitat, P. Lance, M. Suquet, M. Bafleur, J.-P. Laine, A. Peyre-Lavigne, Multi-ring active analogic protection for minority carrier injection suppression in smart power technology, in Proceedings of the 13th International Symposium on Power Semiconductor Devices and ICs (2001), pp. 351–354Google Scholar
  8. 8.
    T.K.H. Starke, P.M. Holland, S. Hussain, W.M. Jamal, P.A. Mawby, P.M. Igic, Highly effective junction isolation structures for PICs based on standard CMOS process. IEEE Trans. Electron Devices 51(7), 1178–1184 (2004)CrossRefGoogle Scholar
  9. 9.
    J. Wittmann, C. Rindfleisch, B. Wicht, Substrate coupling in fast-switching integrated power stages, in IEEE 27th International Symposium on Power Semiconductor Devices & IC’s (ISPSD) (IEEE, New York, 2015), pp. 341–344Google Scholar
  10. 10.
    S.H. Voldman, C.N. Perez, A. Watson, Guard rings: theory, experimental quantification and design, in Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), Sept. 2005 (IEEE, New York, 2005), pp. 1–10Google Scholar
  11. 11.
    B. Murari, F. Bertotti, G.A. Vignola, Smart Power ICs: Technologies and Applications, vol. 6 (Springer Science & Business Media, Berlin, 2002)Google Scholar
  12. 12.
    O. Gonnard, G. Charitat, P. Lance, E. Stefanov, M. Suquet, M. Bafleur, N. Mauran, A. Peyre-Lavigne, Substrate current protection in smart power IC’s, in Proceedings of the IEEE 12th International Symposium on Power Semiconductor Devices and ICs (ISPSD) (2000), pp. 169–172Google Scholar
  13. 13.
    G. Charitat, Isolation issues in smart power integrated circuits, in 23rd International Conference on Microelectronics, vol. 1 (2002), pp. 15–22Google Scholar
  14. 14.
    S. Gupta, J.C. Beckman, S.L. Kosier, Improved latch-up immunity in junction-isolated smart power ICs with unbiased guard ring. IEEE Electron Device Lett. 22(12), 600–602 (2001)CrossRefGoogle Scholar

Copyright information

© Springer International Publishing AG, part of Springer Nature 2018

Authors and Affiliations

  • Pietro Buccella
    • 1
  • Camillo Stefanucci
    • 1
  • Maher Kayal
    • 1
  • Jean-Michel Sallese
    • 2
  1. 1.STI IEL GR-KAÉcole Polytechnique Fédérale de LausanneLausanneSwitzerland
  2. 2.STI IEL EDALBÉcole Polytechnique Fédérale de LausanneLausanneSwitzerland

Personalised recommendations