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TCAD Validation of the Model

  • Pietro Buccella
  • Camillo Stefanucci
  • Maher Kayal
  • Jean-Michel Sallese
Chapter
Part of the Analog Circuits and Signal Processing book series (ACSP)

Abstract

The EPFL substrate lumped device models have been coded in VerilogA and validated by comparison with TCAD simulations. The choice of VerilogA implementation allows to simulate the model in standard circuit simulators as the Cadence Spectre used in this chapter. The Synopsys Sentaurus Device simulator will be used as TCAD software for comparison. Since the EPFL modeling methodology is junction based, the characteristics of diodes from low- to high-current regimes are investigated first before addressing the typical configuration of parasitic BJT in an HV ICs. Results are shown for both the lateral parasitic NPN BJT between two wells and the vertical parasitic PNP BJT where DC, AC, transient, and temperature simulations are reported. Finally, breakdown simulations of basic ESD devices are discussed to demonstrate the capability of the model to simulate unstable snapback behaviors.

References

  1. 1.
    G. Bertrand, C. Delage, M. Bafleur, N. Nolhier, J.-M. Dorkel, Q. Nguyen, N. Mauran, D. Tremouilles, P. Perdu, Analysis and compact modeling of a vertical grounded-base n-p-n bipolar transistor used as ESD protection in a smart power technology. IEEE J. Solid-State Circuits 36(9), 1373–1381 (2001)CrossRefGoogle Scholar
  2. 2.
    M.-D. Ker, K.-C. Hsu, Overview of on-chip electrostatic discharge protection design with SCR-based devices in CMOS integrated circuits. IEEE Trans. Device Mater. Reliab. 5(2), 235–249 (2005)CrossRefGoogle Scholar
  3. 3.
    M.-D. Ker, W.-L. Wu, ESD protection design with the low-leakage-current diode string for RF circuits in BiCMOS SiGe process, in Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD) (2005), pp. 1–7Google Scholar
  4. 4.
    I. Ladany, An analysis of inertial inductance in a junction diode. IRE Trans. Electron Devices 7(4), 303–310 (1960)CrossRefGoogle Scholar
  5. 5.
    S.E. Laux, K. Hess, Revisiting the analytic theory of p-n junction impedance: improvements guided by computer simulation leading to a new equivalent circuit. IEEE Trans. Electron Devices 46(2), 396–412 (1999)CrossRefGoogle Scholar
  6. 6.
    T.J. Maloney, S. Dabral, Novel clamp circuits for IC power supply protection, in Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD) (1995), pp. 1–12Google Scholar
  7. 7.
    J.A. Salcedo, J.J. Liou, Z. Liu, J.E. Vinson, TCAD methodology for design of SCR devices for Electrostatic Discharge (ESD) applications. IEEE Trans. Electron Devices 54(4), 822–832 (2007)CrossRefGoogle Scholar
  8. 8.
    M. Schenkel, Substrate current effects in smart power ICs, PhD thesis, ETH Zürich, Nr. 14925, 2003Google Scholar
  9. 9.
    E. Seebacher, W. Posch, K. Molnar, Z. Huszka, Analog compact modeling for a 20–120 V HV CMOS Technology, in Proceedings of NSTI Nanotechology Conference Trade Show, vol. 3, pp. 720–723 (Nano Science and Technology Institute, Amritsar, 2006)Google Scholar
  10. 10.
    Y. Subramanian, R.B. Darling, Compact modeling of Avalanche breakdown in pn-junctions for computer-aided ESD design (CAD for ESD), in Technical Proceedings of the International Conference on Modeling and Simulation of Microsystems (2001), pp. 205–208Google Scholar
  11. 11.
    J.J.H. van den Biesen, Modelling the inductive behaviour of short-base p-n junction diodes at high forward bias. Solid State Electron. 33(11), 1471–1476 (1990)CrossRefGoogle Scholar
  12. 12.
    V.A. Vashchenko, A. Shibkov, ESD Design for Analog Circuits (Springer, New York, 2010)CrossRefGoogle Scholar
  13. 13.
    J.-S. Yuan, J.J. Liou, W.R. Eisenstadt, A physics-based current-dependent base resistance mode for advanced bipolar transistors. IEEE Trans. Electron Devices 35(7), 1055–1062 (1988)CrossRefGoogle Scholar
  14. 14.
    J. Yuxi, L. Jiao, R. Feng, C. Jialin, Y. Dianxiong, Influence of layout parameters on snapback characteristic for a gate-grounded NMOS device in 0.13-μm silicide CMOS technology. J. Semicond. 30(8), 084007 (2009)Google Scholar

Copyright information

© Springer International Publishing AG, part of Springer Nature 2018

Authors and Affiliations

  • Pietro Buccella
    • 1
  • Camillo Stefanucci
    • 1
  • Maher Kayal
    • 1
  • Jean-Michel Sallese
    • 2
  1. 1.STI IEL GR-KAÉcole Polytechnique Fédérale de LausanneLausanneSwitzerland
  2. 2.STI IEL EDALBÉcole Polytechnique Fédérale de LausanneLausanneSwitzerland

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