TCAD Validation of the Model

  • Pietro Buccella
  • Camillo Stefanucci
  • Maher Kayal
  • Jean-Michel Sallese
Part of the Analog Circuits and Signal Processing book series (ACSP)


The EPFL substrate lumped device models have been coded in VerilogA and validated by comparison with TCAD simulations. The choice of VerilogA implementation allows to simulate the model in standard circuit simulators as the Cadence Spectre used in this chapter. The Synopsys Sentaurus Device simulator will be used as TCAD software for comparison. Since the EPFL modeling methodology is junction based, the characteristics of diodes from low- to high-current regimes are investigated first before addressing the typical configuration of parasitic BJT in an HV ICs. Results are shown for both the lateral parasitic NPN BJT between two wells and the vertical parasitic PNP BJT where DC, AC, transient, and temperature simulations are reported. Finally, breakdown simulations of basic ESD devices are discussed to demonstrate the capability of the model to simulate unstable snapback behaviors.


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Copyright information

© Springer International Publishing AG, part of Springer Nature 2018

Authors and Affiliations

  • Pietro Buccella
    • 1
  • Camillo Stefanucci
    • 1
  • Maher Kayal
    • 1
  • Jean-Michel Sallese
    • 2
  1. 1.STI IEL GR-KAÉcole Polytechnique Fédérale de LausanneLausanneSwitzerland
  2. 2.STI IEL EDALBÉcole Polytechnique Fédérale de LausanneLausanneSwitzerland

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