# Substrate Modeling with Parasitic Transistors

## Abstract

Parasitic substrate currents are strongly related to the propagation of minority carriers inside the chip. Modeling these phenomena requires analytical solutions of transport equations that are available only in the low-current regime. In HV integrated circuits, it is important to solve the charge transport equation for the high-current regime as well, but a closed-form solution of the mathematical model does not exist neither in one nor in three dimensions. In this chapter the substrate modeling methodology based on generalized lumped devices is detailed to overcome this limitation. The approach relies on a discretization scheme for the continuity equations for electrons and holes and introduces a specific concept for meshing the substrate. The mathematical derivation of the nonlinear model is detailed along with the substrate partitioning involving orthogonal cuboids. The transport equations are then converted into virtual voltages and currents that can be solved by circuit simulators. Equivalent circuits for the substrate, the junctions, and the contacts are then proposed, also including time-dependent effects.

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