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Design Challenges in High-Voltage ICs

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Parasitic Substrate Coupling in High Voltage Integrated Circuits

Part of the book series: Analog Circuits and Signal Processing ((ACSP))

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Abstract

This chapter presents the design challenges regarding substrate couplings due to parasitic substrate bipolar transistors in HV ICs. The basic characteristics of HV technologies and substrate parasitic bipolar structures are identified and organized to demonstrate the main trade-offs that designers have to face. Moreover, representative circuit topologies are analyzed to show how such substrate parasitic transistors can be activated in real-world applications, pointing out the usefulness of an adequate substrate model to avoid failures that are hard to predict. The final part of this chapter is devoted to the identification of specific cases where substrate currents adversely affect the functionality of circuits.

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Authors and Affiliations

  1. STI IEL GR-KA, École Polytechnique Fédérale de Lausanne, Lausanne, Switzerland

    Pietro Buccella, Camillo Stefanucci & Maher Kayal

  2. STI IEL EDALB, École Polytechnique Fédérale de Lausanne, Lausanne, Switzerland

    Jean-Michel Sallese

Authors
  1. Pietro Buccella
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  2. Camillo Stefanucci
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  3. Maher Kayal
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  4. Jean-Michel Sallese
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Buccella, P., Stefanucci, C., Kayal, M., Sallese, JM. (2018). Design Challenges in High-Voltage ICs. In: Parasitic Substrate Coupling in High Voltage Integrated Circuits. Analog Circuits and Signal Processing. Springer, Cham. https://doi.org/10.1007/978-3-319-74382-0_2

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  • DOI: https://doi.org/10.1007/978-3-319-74382-0_2

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  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-74381-3

  • Online ISBN: 978-3-319-74382-0

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