Overview of Parasitic Substrate Coupling

  • Pietro Buccella
  • Camillo Stefanucci
  • Maher Kayal
  • Jean-Michel Sallese
Part of the Analog Circuits and Signal Processing book series (ACSP)


Major issues related to the parasitic substrate current in integrated circuits and related engineering solutions are introduced in this chapter. The main cause for electrical couplings taking place in the substrate has been attributed to the activation of parasitic transistors. These devices can be identified from the layout, but still the analysis of parasitic substrate current cannot be restricted to the analysis of parasitic transistors only. In essence, a predictive analysis of substrate coupling mechanisms requires that minority and majority carriers are taken into account in circuit simulators. One could argue that minority carriers are already included in compact models. For instance, the model for the bipolar transistor does include the minority carriers. But these minority carriers are never “propagated” between the different devices, and, for instance, simulating a np-pn connection of diodes does not predict the characteristics of a BJT. An overview of the strategies proposed so far to simulate parasitic signals in IC substrates is presented in the state-of-the-art section. In general, circuit designers use specific tools to fix severe substrate coupling mechanisms, and, to avoid failures and costly redesign processes, this analysis is done during the design phase of the circuit.


  1. 1.
    A. Hastings, The Art of Analog Layout (Prentice Hall, Upper Saddle River, 2005)Google Scholar
  2. 2.
    R.J. Widlar, Controlling substrate currents in junction-isolated ICs. IEEE J. Solid State Circuits 26(8), 1090–1097 (1991)CrossRefGoogle Scholar
  3. 3.
    A. Abdel-Ghaffar, M. Ismail, Substrate Noise Coupling in RFICs (Springer Science & Business Media, New York, 2008)Google Scholar
  4. 4.
    T.A. Johnson, R.W. Knepper, V. Marcello, W. Wang, Chip substrate resistance modeling technique for integrated circuit design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 3(2), 126–134 (1984)CrossRefGoogle Scholar
  5. 5.
    B. Nauta, G. Hoogzaad, Substrate bounce in mixed-mode CMOS IC’s, in Workshop on Substrate Noise Coupling in Mixed-Signal IC’s (1998), pp. 201–213Google Scholar
  6. 6.
    I. Zheng, H. Zhao, J. Yang, W. Li, W. Li, L. Wei, C. Wang, Analysis of a bandgap circuit DC shift caused by substrate noise generated by power switches, in 8th International Conference on Solid-State and Integrated Circuit Technology (ICSICT), Oct 2006, pp. 1718–1720Google Scholar
  7. 7.
    W. Horn, H. Zitta, A robust smart power bandgap reference circuit for use in an automotive environment, in Proceedings of the 27th European Solid-State Circuits Conference (ESSCIRC), Sept 2001, pp. 217–220Google Scholar
  8. 8.
    D.K. Su, M.J. Loinaz, S. Masui, B.A. Wooley, Experimental results and modeling techniques for substrate noise in mixed-signal integrated circuits. IEEE J. Solid State Circuits 28(4), 420–430 (1993)CrossRefGoogle Scholar
  9. 9.
    B. Murari, F. Bertotti, G.A. Vignola, A. Andreini, Smart Power ICs: Technologies and Applications (Springer-Verlag GmbH, Berlin, 1996)CrossRefGoogle Scholar
  10. 10.
    O. Gonnard, G. Charitat, P. Lance, E. Stefanov, M. Suquet, M. Bafleur, N. Mauran, A. Peyre-Lavigne, Substrate current protection in smart power IC’s, in Proceedings of the IEEE 12th International Symposium on Power Semiconductor Devices and ICs (ISPSD) (2000), pp. 169–172Google Scholar
  11. 11.
    M. Schenkel, Substrate current effects in smart power ICs. PhD thesis, ETH Zürich, Nr. 14925, 2003Google Scholar
  12. 12.
    M. Schenkel, P. Pfaeffli, W. Wilkening, D. Aemmer, W. Fichtner, Transient minority carrier collection from the substrate in smart power design, in Proceedings of the 31st European Solid-State Device Research Conference (ESSDERC), Sept 2001, pp. 411–414Google Scholar
  13. 13.
    E. Gnani, V. Giudicissi, R. Vissarion, C. Contiero, M. Rudan, Automatic 2-D and 3-D simulation of parasitic structures in smart-power integrated circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(7), 791–798 (2002)CrossRefGoogle Scholar
  14. 14.
    M. Kollmitzer, M. Olbrich, E. Barke, Analysis and modeling of minority carrier injection in deep-trench based BCD technologies, in 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME), June 2013, pp. 245–248Google Scholar
  15. 15.
    M. Corradin, A. Sangiovanni-Vincentelli, E. Charbon, Modeling minority carrier diffusion through substrate in SMART power ICs, in IEEE Behavioral Modeling and Simulation (BMAS) (2005)Google Scholar
  16. 16.
    J. Oehmen, L. Hedrich, M. Olbrich, E. Barke, A methodology for modeling lateral parasitic transistors in smart power ICs, in IEEE Behavioral Modeling and Simulation (BMAS), Sept 2005, pp. 19–24Google Scholar
  17. 17.
    F. Lo Conte, J.-M. Sallese, M. Kayal, Smart power IC simulation of substrate coupled current due to majority and minority carriers transports, in IEEE International Conference on IC Design and Technology (ICICDT), June 2010, pp. 168–171Google Scholar
  18. 18.
    F. Lo Conte, J.-M. Sallese, M. Kayal, Modeling methodology of high-voltage substrate minority and majority carrier injections, in Proceedings of the European Solid-State Device Research Conference (ESSDERC), Sept 2010, pp. 194–197Google Scholar
  19. 19.
    C. Stefanucci, P. Buccella, M. Kayal, J.-M. Sallese, Spice-compatible modeling of high injection and propagation of minority carriers in the substrate of smart power {ICs}. Solid State Electron. 105, 21–29 (2015)CrossRefGoogle Scholar
  20. 20.
    J.G. Linvill, Lumped models of transistors and diodes. Proc. IRE 46(6), 1141–1152 (1958)CrossRefGoogle Scholar
  21. 21.
    C.T. Sah, The equivalent circuit model in solid-state electronics-III: conduction and displacement currents. Solid State Electron. 13(12), 1547–1575 (1970)CrossRefGoogle Scholar
  22. 22.
    S.E. Laux, K. Hess, Revisiting the analytic theory of p-n junction impedance: improvements guided by computer simulation leading to a new equivalent circuit. IEEE Trans. Electron Devices 46(2), 396–412 (1999)CrossRefGoogle Scholar
  23. 23.
    A.-G. Bajenaru, C. Boianceanu, G. Brezeanu, Investigation of electro-thermal behaviour of a linear voltage regulator and its protection circuits by simulator coupling, in International Semiconductor Conference (CAS), vol. 2, Oct 2013, pp. 237–240Google Scholar
  24. 24.
    A.Z. Wang, C.H. Tsay, A new design methodology using simulation for on-chip ESD protection designs for integrated circuits, in 5th International Conference on Solid-State and Integrated Circuit Technology (1998), pp. 509–512Google Scholar
  25. 25.
    H. Feng, G. Chen, R. Zhan, Q. Wu, X. Guan, H. Xie, A.Z.H. Wang, R. Gafiteanu, A mixed-mode ESD protection circuit simulation-design methodology. IEEE J. Solid State Circuits 38(6), 995–1006 (2003)CrossRefGoogle Scholar
  26. 26.
    F.J.R. Clement, E. Zysman, M. Kayal, M. Declercq, LAYIN: toward a global solution for parasitic coupling modeling and visualization, in Proceedings of the IEEE Custom Integrated Circuits Conference (CICC), May 1994, pp. 537–540Google Scholar
  27. 27.
    I.L. Wemple, A.T. Yang, Integrated circuit substrate coupling models based on Voronoi tessellation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(12), 1459–1469 (1995)CrossRefGoogle Scholar
  28. 28.
    K.J. Kerns, I.L. Wemple, A.T. Yang, Stable and efficient reduction of substrate model networks using congruence transforms, in IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Nov 1995, pp. 207–214Google Scholar
  29. 29.
    A. Koukab, K. Banerjee, M. Declercq, Modeling techniques and verification methodologies for substrate coupling effects in mixed-signal system-on-chip designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(6), 823–836 (2004)CrossRefGoogle Scholar
  30. 30.
    Mentor Graphics. Calibre®; percGoogle Scholar

Copyright information

© Springer International Publishing AG, part of Springer Nature 2018

Authors and Affiliations

  • Pietro Buccella
    • 1
  • Camillo Stefanucci
    • 1
  • Maher Kayal
    • 1
  • Jean-Michel Sallese
    • 2
  1. 1.STI IEL GR-KAÉcole Polytechnique Fédérale de LausanneLausanneSwitzerland
  2. 2.STI IEL EDALBÉcole Polytechnique Fédérale de LausanneLausanneSwitzerland

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