Abstract
The effective cache consistency protocol plays an important role in improving the processor performance. This paper designed an improved architecture of consistency protocol for multi-core environment, adding the D-Cache virtual bus to achieve the point-to-point consistency transaction transmission which avoided the bus idle phenomenon caused by the polling query method that the broadcast consistency transaction must be observed. The experimental results show that the architecture can improve the bus utilization.
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Acknowledgments
This work is supported by Research on Compiling Technology Based on FPGA Reconfigurable Hybrid System (No. 61003036). The authors would like to thank all of the co-authors of this work.
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© 2018 ICST Institute for Computer Sciences, Social Informatics and Telecommunications Engineering
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Tian, Q., Li, J., Zheng, F., Zhao, S. (2018). A Cache Consistency Protocol with Improved Architecture. In: Sun, G., Liu, S. (eds) Advanced Hybrid Information Processing. ADHIP 2017. Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering, vol 219. Springer, Cham. https://doi.org/10.1007/978-3-319-73317-3_3
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DOI: https://doi.org/10.1007/978-3-319-73317-3_3
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