An Efficient Hardware Architecture for Multilayer Spiking Neural Networks

  • Yuling Luo
  • Lei Wan
  • Junxiu Liu
  • Jinlei Zhang
  • Yi Cao
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 10639)


Spiking Neural Network (SNN) is the most recent computational model that can emulate the behaviors of biological neuron system. This paper highlights and discusses an efficient hardware architecture for the hardware SNNs, which includes a layer-level tile architecture (LTA) for the neurons and synapses, and a novel routing architecture (NRA) for the interconnections between the neuron nodes. In addition, a visualization performance monitoring platform is designed, which is used as functional verification and performance monitoring for the SNN hardware system. Experimental results demonstrate that the proposed architecture is feasible and capable of scaling to large hardware multilayer SNNs.


Spiking Neural Networks Hardware architecture FPGA 



This research was supported by the National Natural Science Foundation of China under grants 61603104 and 61661008, the Guangxi Natural Science Foundation under grants 2015GXNSFBA139256 and 2016GXNSFCA380017, the funding of Overseas 100 Talents Program of Guangxi Higher Education, the Research Project of Guangxi University of China under grant KY2016YB059, Guangxi Key Lab of Multi-source Information Mining & Security under grant MIMS15-07, the Doctoral Research Foundation of Guangxi Normal University, the Research Project of Guangxi Centre of Humanities & Social Sciences - Ecological Environment Forecast and Harnessing in Ecologically Vulnerable Region of Pearl River and Xijiang Economic Zone (ZX2016030), and the Innovation Project of Guangxi Graduate Education (YCSZ2016034).


  1. 1.
    Moctezuma, J.C., McGeehan, J.P., Nunez-Yanez, J.L.: Biologically compatible neural networks with reconfigurable hardware. Microprocessors Microsyst. 39(8), 693–703 (2015)CrossRefGoogle Scholar
  2. 2.
    Beuler, M., Tchaptchet, A., Bonath, W., Postnova, S., Braun, H.A.: Real-time simulations of synchronization in a conductance-based neuronal network with a digital FPGA hardware-core. Artif. Neural Netw. Mach. Learn. 7552(6), 97–104 (2012)Google Scholar
  3. 3.
    Pande, S., Morgan, F., Cawley, S., Bruintjes, T., Smit, G., McGinley, B., Carrillo, S., Harkin, J., McDaid, L.: Modular neural tile architecture for compact embedded hardware spiking neural network. Neural Process. Lett. 38(2), 131–153 (2013)CrossRefGoogle Scholar
  4. 4.
    Carrillo, S., Harkin, J., Mcdaid, L., Pande, S., Cawley, S., Mcginley, B., Morgan, F.: Advancing interconnect density for spiking neural network hardware implementations using traffic-aware adaptive network-on-chip routers. Neural Netw. 33(9), 42–57 (2012)CrossRefGoogle Scholar
  5. 5.
    Schemmel, J., Fieres, J., Meier, K.: Wafer-scale integration of analog neural networks. In: Proceedings of the International Joint Conference on Neural Networks, pp. 431–438 (2008)Google Scholar
  6. 6.
    Carrillo, S., Harkin, J., McDaid, L.J., Morgan, F., Pande, S., Cawley, S., McGinley, B.: Scalable hierarchical network-on-chip architecture for spiking neural network hardware implementations. IEEE Trans. Parallel Distrib. Syst. 24(12), 2451–2461 (2013)CrossRefGoogle Scholar
  7. 7.
    Maguire, L.P., McGinnity, T.M., Glackin, B., Ghani, A., Belatreche, A., Harkin, J.: Challenges for large-scale implementations of spiking neural networks on FPGAs. Neurocomputing 71(1–3), 13–29 (2007)CrossRefGoogle Scholar
  8. 8.
    Iakymchuk, T., Rosado, A., Frances, J.V., Batallre, M.: Fast spiking neural network architecture for low-cost FPGA devices. In: 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip, pp. 1245–1248 (2012)Google Scholar
  9. 9.
    Tsodyks, M., Pawelzik, K., Markram, H.: Neural networks with dynamic synapses. Neural Comput. 10(4), 821–835 (1998)CrossRefGoogle Scholar
  10. 10.
    Stein, R.: A theoretical analysis of neuronal variability. Biophys. J. 5(2), 173–194 (1965)CrossRefGoogle Scholar
  11. 11.
    Wade, J.J., McDaid, L.J., Santos, J.A., Sayers, H.M.: SWAT: a spiking neural network training algorithm for classification problems. IEEE Trans. Neural Netw. 21(11), 1817–1830 (2010)CrossRefGoogle Scholar
  12. 12.
    Fidjeland, A.K., Shanahan, M.P.: Accelerated simulation of spiking neural networks using GPUs. In: Proceedings of the International Joint Conference on Neural Networks (IJCNN), pp. 1–8 (2010)Google Scholar

Copyright information

© Springer International Publishing AG 2017

Authors and Affiliations

  • Yuling Luo
    • 1
  • Lei Wan
    • 1
  • Junxiu Liu
    • 1
  • Jinlei Zhang
    • 1
  • Yi Cao
    • 2
  1. 1.Guangxi Key Lab of Multi-source Information Mining and Security, Faculty of Electronic EngineeringGuangxi Normal UniversityGuilinChina
  2. 2.Department of Business Transformation and Sustainable Enterprise, Surrey Business SchoolUniversity of SurreySurreyUK

Personalised recommendations