Abstract
The technique of binary data sequence generator based on LFSR is used a variety of cryptographic applications and for designing an encoder/decoder in different communication channel. It is more important to test and verify by implementing on any hardware device to get a better effective result. As FPGA is used to implement any logical function for faster prototype development, it is necessary to implement the existing LFSR design on FPGA to test and verify the result of simulation and synthesis between different lengths. The total number of random states generated on LFSR depends on the feedback polynomial. The binary data generator is implemented using an LFSR shift register. This is a 23-bit shift register. Random Number Generator allows you to generate a random number with the selected length. The maximum length is 223−1.
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References
Luby, M.: Pseudo randomness and Cryptographic Applications. Princeton University Press, Princeton (1996)
Hao, J., Li, Z,: On the production of pseudo random Numbers in Cryptogrzphy. J. Chzngehou Teach. Coll. Technol. 7 (2001)
L’Ecuyer, P.: Random numbers for simulation. Commun. ACM 33, 10 (1990)
Katti, R.S. Srinivasan, S.K.: Efficient hardware implementation of a new pseudo-random bit sequence generator. In: IEEE International Symposium on Circuits and Systems, ISCAS 2009 (2009)
Goresky, M., Klapper, A.M.: Fibonacci and Galois representations of feedback-with-carry shift registers. IEEE Trans. Inf. Theory 48, 2826–2836 (2002)
Brown, S., Vranesic, Z.: Fundamental of Digital Logic Design with VHDL, 2nd edn. McGraw Hill
Panda Amit, K., Rajput, P., Shukla, B.: Design of multi bit LFSR PNRG and performance comparison on FPGA usingVHDL‖. Int. J. Adv. Eng. Technol. (IJAET) 3(1), 566–571 (2012)
Bhasker, J.: A VHDL Primer. P T R Prentice Hall, Englewood Cliffs (2013)
Hao, J., Li, Z.: FPGA design flow based on a variety of EDA tools. Micro-comput. Inf. 11-2(23), 201–203 (2007)
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Benzaima, M., Mohammed, M., Abdessadek, A., El Hore, A. (2018). Implementing of a Binary Data Generator on a FPGA Card. In: Ezziyyani, M., Bahaj, M., Khoukhi, F. (eds) Advanced Information Technology, Services and Systems. AIT2S 2017. Lecture Notes in Networks and Systems, vol 25. Springer, Cham. https://doi.org/10.1007/978-3-319-69137-4_44
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DOI: https://doi.org/10.1007/978-3-319-69137-4_44
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