Instruction Set Architectures for Quantum Processing Units

Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 10524)


Progress in quantum computing hardware raises questions about how these devices can be controlled, programmed, and integrated with existing computational workflows. We briefly describe several prominent quantum computational models, their associated quantum processing units (QPUs), and the adoption of these devices as accelerators within high-performance computing systems. Emphasizing the interface to the QPU, we analyze instruction set architectures based on reduced and complex instruction sets, i.e., RISC and CISC architectures. We clarify the role of conventional constraints on memory addressing and instruction widths within the quantum computing context. Finally, we examine existing quantum computing platforms, including the D-Wave 2000Q and IBM Quantum Experience, within the context of future ISA development and HPC needs.


Quantum Accelerator Instruction set architecture qubit 


  1. 1.
    Grover, L.K.: A fast quantum mechanical algorithm for database search. In: STOC 1996, pp. 212–219 (1996)Google Scholar
  2. 2.
    Hen, I.: Realizable quantum adiabatic search [quant-ph] arXiv:1612.06012 (2016)
  3. 3.
    Nielsen, Michael A., Chuang, Isaac L.: Quantum Computation and Quantum Information: 10th Anniversary Edition. Cambridge University Press, New York (2011)zbMATHGoogle Scholar
  4. 4.
    IBM Research Quantum Experience.
  5. 5.
    Farhi, E., Goldstone, J., Gutmann, S., Sipser, M.: Quantum computation by adiabatic evolution. Report MIT-CTP-2936, Massachusetts Institute of Technology (2000)Google Scholar
  6. 6.
    The D-Wave 2000Q™System.
  7. 7.
    Hamilton, K.E., Humble, T.S.: Identifying the Minor Set Cover of Dense Connected Bipartite Graphs via Random Matching Edge Sets (2016). arXiv:1612.07366
  8. 8. Global Supercomputing Capacity Creeps Up as Petascale Systems Blanket Top 100. (2016)Google Scholar
  9. 9.
    Britt, K.A., Humble, T.S.: High-performance computing with quantum processing units. J. Emerg. Technol. Comput. Syst. 13(3) (2017). Article 39Google Scholar
  10. 10.
    Fu, X., Riesebos, L., Lao, L., Almudever, C.G., Sebastiano, F., Versluis, R., Charbon, E., Bertels, K.: A heterogeneous quantum computer architecture. In: Proceedings of the ACM International Conference on Computing Frontiers (CF 2016), pp. 323–330. ACM, New York (2016)Google Scholar
  11. 11.
  12. 12.
    Patterson, David A.: Reduced instruction set computers. Commun. ACM 28(1), 8–21 (1985)MathSciNetCrossRefGoogle Scholar
  13. 13.
    George, A.D.: An overview of RISC vs. CISC. In: Proceedings of The Twenty-Second Southeastern Symposium on System Theory, pp. 436–438 (1990)Google Scholar
  14. 14.
    Calderbank, A.R., Shor, Peter W.: Good quantum error-correction codes exist. Phys. Rev. A 54(2), 1098–1105 (1996)CrossRefGoogle Scholar
  15. 15.
    Hales, L., Hallgren, S.: An improved quantum Fourier transform algorithm and applications. In: Proceedings 41st Annual Symposium on Foundations of Computer Science, pp. 5115–525 (2000)Google Scholar
  16. 16.
    Britt, K.A., Humble, T.S.: QUBO computational reliability via hamiltonian engineering. In: Adiabatic Quantum Computing Conference (2016)Google Scholar
  17. 17.
    Harrow, A.W., Hassidim, A., Lloyd, S.: Quantum algorithm for linear systems of equations. Phys. Rev. Lett. 15(103), 150502 (2009)MathSciNetCrossRefGoogle Scholar

Copyright information

© Springer International Publishing AG 2017

Authors and Affiliations

  1. 1.Quantum Computing Institute, Oak Ridge National LaboratoryOak RidgeUSA

Personalised recommendations