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TeLEx: Passive STL Learning Using Only Positive Examples

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Runtime Verification (RV 2017)

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We propose a novel passive learning approach, TeLEx, to infer signal temporal logic formulas that characterize the behavior of a dynamical system using only observed signal traces of the system. The approach requires two inputs: a set of observed traces and a template Signal Temporal Logic (STL) formula. The unknown parameters in the template can include time-bounds of the temporal operators, as well as the thresholds in the inequality predicates. TeLEx finds the value of the unknown parameters such that the synthesized STL property is satisfied by all the provided traces and it is tight. This requirement of tightness is essential to generating interesting properties when only positive examples are provided and there is no option to actively query the dynamical system to discover the boundaries of legal behavior. We propose a novel quantitative semantics for satisfaction of STL properties which enables TeLEx to learn tight STL properties without multidimensional optimization. The proposed new metric is also smooth. This is critical to enable use of gradient-based numerical optimization engines and it produces a 30\(\times \)–100\(\times \) speed-up with respect to the state-of-art gradient-free optimization. The approach is implemented in a publicly available tool.

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This work is supported in part by DARPA under contract FA8750-16-C-0043 and NSF grant CNS-1423298.

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Correspondence to Susmit Jha .

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Jha, S., Tiwari, A., Seshia, S.A., Sahai, T., Shankar, N. (2017). TeLEx: Passive STL Learning Using Only Positive Examples. In: Lahiri, S., Reger, G. (eds) Runtime Verification. RV 2017. Lecture Notes in Computer Science(), vol 10548. Springer, Cham.

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