Integrated circuits (IC) is a multi-disciplinary and multi-level industry, which is composed of product definition, system design, circuit design, electronic design automation (EDA), chip fabrication, package, and test.


  1. 1.
    I.A. Young, E. Mohammed, J.T.S. Liao, A.M. Kern, S. Palermo, B.A. Block, M.R. Reshotko, P.L.D. Chang, Optical I/O technology for tera-scale computing solid-state circuits. IEEE J. 45(1), 235–248 (2010)Google Scholar
  2. 2.
    ATT: ATT u-verse-digital TV, high speed internet and voice (2012),
  3. 3.
    P. Crombez, Full reconfigurable analog baseband circuits for multimode radios, KU Leuven Thesis (2009)Google Scholar
  4. 4.
    S. McGlaun, Tablet shipments to outpace total PC shipments in Q4 2013 says IDC,
  5. 5.
    F. Wanlass, Low stand-by power complementary field effect circuitry, US Patent 3356858 (1967)Google Scholar
  6. 6.
    M. Gordon, Cramming more components onto integrated circuits, Electronics Magazine (1965)Google Scholar
  7. 7.
    W. Zhao, Y. Cao, New generation of predictive technology model for sub-45 nm early design exploration. IEEE Trans. Electron Devices 53(11), 2816–2823 (2006)Google Scholar
  8. 8.
    W. Sansen, Analog design essentials (Springer, 2008)Google Scholar
  9. 9.
    K. Cornelissens, Delta-Sigma A/D converter design in nanoscale CMOS, KU Leuven Thesis (2010)Google Scholar
  10. 10.
    ITRS, International technology roadmap for semiconductors (2012),,2012
  11. 11.
    J.L. Hogan, Developments of the heterodyne receiver. Proc. Inst. Radio Eng. 3(3), 249–259 (1915)Google Scholar
  12. 12.
    A.A. Abidi, Direct-conversion radio transceivers for digital communications. IEEE J. Solid-State Circ. 30(12), 1399–1410 (1995)Google Scholar
  13. 13.
    J. Crols, M.S.J. Steyaert, single-chip 900 MHz CMOS receiver front-end with a high performance low-IF topology. IEEE J. Solid-State Circuits 30(12), 1483–1492 (1995)Google Scholar
  14. 14.
    T. Chalvatzis, T.O. Dickson, S.P. Voinigescu, 2-GHz direct-sampling delta-sigma tunable receiver with 40-GHz sampling clock and on-chip PLL, in 2007 IEEE Symposium on VLSI Circuits (2007), pp. 54–55Google Scholar
  15. 15.
    B. Grayver, E. Daneshrad, VLSI implementation of a 100-\(\upmu \)w multirate FSK receiver. IEEE J. Solid-State Circuits, 36(11), 1821–1828 (2001)Google Scholar

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© Springer International Publishing AG 2018

Authors and Affiliations

  1. 1.Graduate School at ShenzhenTsinghua UniversityShenzhenChina
  2. 2.Zhongguancun Dongsheng Technology ParkAnalog Devices, Inc.BeijingChina
  3. 3.Departement Elektrotechniek, ESAT-MICASKatholieke Universiteit LeuvenLeuvenBelgium

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