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Conclusions

  • Hani Saleh
  • Nourhan Bayasi
  • Baker Mohammad
  • Mohammed Ismail
Chapter
Part of the Analog Circuits and Signal Processing book series (ACSP)

Abstract

The chapter concludes the book by summarizing the presented system and its implementation results.

Keywords

ECG signal processor (ESP) 65 nm CMOS process 

In this work, a fully integrated digital ECG signal processor (ESP) for the prediction of ventricular arrhythmia that combines a unique set of ECG features with Naive Bayes was presented. Real-time and adaptive techniques for the detection and delineation of the P-QRS-T waves were utilized to extract the fiducial points. These adaptive techniques gave the system robustness in dealing with ECG signal variations with high sensitivity and precision. They employed adaptive search windows and thresholds based on previously detected values to identify each wave with its morphology (monophasic, inverted, biphasic). Furthermore, seven features which represent different intervals of the ECG signal were extracted and used as input to the Naive Bayes to classify each heartbeat as normal or abnormal. The combination of these features has never been used in any previous detection or prediction system yet proved to be highly efficient in predicting VT/VF. The proposed system was tested using two databases of heart recordings from the MIT PhysioNet and the American Heart Association (AHA) and verified under different scenarios. The system achieved an outstanding capability of predicting the arrhythmia up to 3 h before the onset. Based on Matlab testing results, an accuracy (ACC) of 99.98%, recall (SE) of 98.9%, and precision (P) of 99% were obtained on the out-of-sample validation data by tenfold cross validation with 3 s window size.

The ESP processor was implemented using the GlobalFoundries 65 nm low-power CMOS process. Standard cell-based ASIC design flow was used and included: Verilog RTL coding, verification, synthesis, floor planning, placement, routing, and chip finishing. The ESP occupied 0.112 mm2 area and consumed 2.78 μW power at an operating frequency of 10 kHz at 1.2 V. The small area, low power, and high performance of the proposed ESP make it suitable for inclusion in system on chips (SoCs) targeting wearable mobile medical devices.

Copyright information

© Springer International Publishing AG 2018

Authors and Affiliations

  • Hani Saleh
    • 1
  • Nourhan Bayasi
    • 2
  • Baker Mohammad
    • 1
  • Mohammed Ismail
    • 3
  1. 1.Department of Electronic EngineeringKhalifa University of Science, Technology and ResearchAbu DhabiUnited Arab Emirates
  2. 2.Department of Electrical and Computer EngineeringKhalifa University of Science, Technology and ResearchAbu DhabiUnited Arab Emirates
  3. 3.Department of Electrical and Computer Engineering DepartmentKhalifa University of Science, Technology and ResearchAbu DhabiUnited Arab Emirates

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