The chapter introduces the hardware design of an automated system for prediction and detection of cardiac arrhythmias especially VT/VF. The system’s architecture is presented, the preprocessing stage is explained, then the system control scheme is introduced, and next the specifics for the realization of the QRS complex, the P and T wave signal delineation, and the classification systems are presented. The chapter is concluded by listing the ASIC implementation results of the given system in 65-nm GlobalFoundries process.
Hardware implementation ASIC implementation 65 nm Testbench Simulation Finite-State Machine (FSM) Synthesis Floor Plan, Place and Route and Chip Finishing
This is a preview of subscription content, log in to check access.
J. Pan, W.J. Tompkins, A real-time QRS detection algorithm. IEEE Trans. Biomed. Eng. 32(3), 230–236 (1985)CrossRefGoogle Scholar
N. Thakor, J. Webster, W. Tompkins, Optimal qrs detector. Med. Biol. Eng. Comput. 21(3), 343–350 (1983)CrossRefGoogle Scholar