Image Reconstruction Using Novel Two-Dimensional Fourier Transform

  • S. Kala
  • S. Nalesh
  • Babita R. Jose
  • Jimson Mathew
Chapter
Part of the Studies in Computational Intelligence book series (SCI, volume 730)

Abstract

Reconstruction of a signal from its subset is used in various contexts in the field of signal processing. Image reconstruction is one such example which finds widespread application in face recognition, medical imaging, computer vision etc. Image reconstruction is computationally complex, and efficient implementations need to exploit the parallelism inherent in this operation. Discrete Fourier Transform (DFT) is a widely used technique for image reconstruction. Fast Fourier Transform (FFT) algorithms are used to compute DFTs efficiently. In this paper we propose a novel two dimensional (2D) Fast Fourier Transform technique for efficient reconstruction of a 2D image. The algorithm first applies 1D FFT based on radix-\(4^n\) along the rows of the image followed by same FFT operation along columns, to obtain a 2D FFT. Radix-\(4^n\) technique used here provides significant savings in memory required in the intermediate stages and considerable improvement in latency. The proposed FFT algorithm can be easily extended to three dimensional and higher dimensional FFTs. Simulated results for image reconstruction based on this technique are presented in the paper. 64 point FFT based on radix-\(4^3\) has been implemented using 130nm CMOS technology and operates at a maximum clock frequency of 350 MHz.

References

  1. 1.
    Proakis, J.G., Manolakis, D.G.: Digital Signal Processing Principles, Algorithms and Applications. Prentice-Hall (1996)Google Scholar
  2. 2.
    Yu, C.-L., Chakrabarti, C., Park, S., Narayanan, V.: Bandwidth-intensive FPGA architecture for multi-dimensional DFT. In: IEEE International Conference on Acoustics, Speech, Signal Processing, pp. 1486–1489 (2010)Google Scholar
  3. 3.
    Gold, B., Rabiner, L.R.: Theory and Application of Digital Signal Processing. Prentice-Hall (1975)Google Scholar
  4. 4.
    Corts, A., Vlez, I., Zalbide, I., Irizar, A., Sevillano, J.F.: An FFT core for DVB-T/DVB-H receivers. VLSI Design (2008)Google Scholar
  5. 5.
    He, S., Torkelson, M.: A new approach to pipeline FFT processor. In: 10th International Parallel Processing Symposium, IPPS ’96, pp. 766–770 (1996)Google Scholar
  6. 6.
    He, S., Torkelson, M.: Designing pipeline FFT processor for OFDM (de)modulation. Signals Syst. Electron. (1998)Google Scholar
  7. 7.
    Frigo, M., Johnson, S.: FFTW: an adaptive software of the FFT. In: IEEE International Conference on Acoustics, Speech, and Signal Processing, pp. 1381–1384 (1998)Google Scholar
  8. 8.
    Pschel, M., et al.: SPIRAL: code generation for DSP transforms. Proc. IEEE 93(2), 232–275 (2005)CrossRefGoogle Scholar
  9. 9.
    D’Alberto, P., et al.: Generating FPGA accelerated DFT libraries. In: IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), pp. 173–184 (2007)Google Scholar
  10. 10.
    Dillon, T.: Two virtex-II FPGAs deliver fastest, cheapest, best high-performance image processing system. Xilinx Xcell J. 41, 70–73 (2001)Google Scholar
  11. 11.
    Chen, R., Prasanna, V.K.: Energy optimizations for FPGA-based 2-D FFT architecture. In: IEEE High Performance Extreme Computing Conference (HPEC) (2014)Google Scholar
  12. 12.
    Yu, C.-L., Kim, J.-S., Deng, L., Kestur, S., Narayanan, V., Chakrabarti, C.: FPGA architecture for 2D discrete Fourier Transform based on 2D decomposition for large-sized data. Signal Process. Syst. 64(1), 109–122 (2011)Google Scholar
  13. 13.
    Kee, H., Bhattacharyya, S.S., Petersen, N., Kornerup, J.: Resource-efficient acceleration of 2-Dimensional Fast Fourier Transform computations on FPGAs. In: International Conference on Distributed Smart Cameras, Como, Italy (2009)Google Scholar
  14. 14.
    Wang, W., Duan, B., Zhang, C., Zhang, P., Sun, N.: Accelerating 2D FFT with non-power-of-two problem size on FPGA. In: International Conference on Reconfigurable Computing (2010)Google Scholar
  15. 15.
    Kala, S., Nalesh, S., Arka, M., Nandy, S.K., Narayan, R.: High throughput, low latency, memory optimized 64K point FFT architecture using novel radix-4 butterfly unit. In: IEEE International Symposium on Circuits and Systems, ISCAS, pp. 3034–3037 (2013)Google Scholar
  16. 16.
    Chidambaram, R.: A scalable and high-performance FFT processor, optimized for UWB-OFDM. M.S. thesis, Delft University of Technology (2005)Google Scholar
  17. 17.
    Babionitakis, K., Chouliaras, V.A., Manolopoulos, K., Nakos, K., Reisis, D., Vlassopoulos, N.: Fully systolic FFT architecture for Giga-sample applications. J. Signal Process. Syst. 58, 281–299 (2010)Google Scholar
  18. 18.
    Kala, S., Nalesh, S., Nandy, S.K., Narayan, R.: Scalable and energy efficient, dynamically reconfigurable Fast Fourier Transform architecture. J. Low Power Electron. 11(3), 426–435 (2015)CrossRefGoogle Scholar
  19. 19.
    Li, N., ASIC FFT Processor for MB-OFDM UWB System: M.Sc. thesis, Delft University of Technology (2008)Google Scholar
  20. 20.
    Lin, Y.N., Liu, H.Y., Lee, C.Y.: A 1-GS/s FFT/IFFT processor for UWB applications. IEEE J. Solid State Circuits 40(8) (2005)Google Scholar
  21. 21.
    Lin, Y.-W., Liu, H.-Y., Lee, C.-Y.: A dynamic scaling FFT processor for DVB-T applications. IEEE J. Solid State Circuits 39(11) (2004)Google Scholar
  22. 22.
    Maharatna, K., Grass, E., Jagdhold, U.: A 64-point Fourier Transform chip for high-speed wireless LAN application using OFDM. IEEE J. Solid State Circuits 39(3), 484–493 (2004)Google Scholar
  23. 23.
    He, S., Torkelson, M.: Designing pipeline FFT processor for OFDM (de)modulation. Signals Syst. Electron. (1998)Google Scholar
  24. 24.
    Lin, C.-T., Yu, Y.-C.: Cost-effective pipeline FFT/IFFT VLSI architecture for DVB-H system. In: National Symposium on Telecommunications (2007)Google Scholar
  25. 25.
    Lin, C.T., Yu, Y.C., Van, L.D.: A low power 64-point FFT/IFFT design for IEEE 802.11a WLAN application. In: IEEE International Symposium on Circuits and Systems, ISCAS, pp. 4523–4526 (2006)Google Scholar
  26. 26.
    Rodrguez-Ramos, J.M., Magdaleno Castell, E., Domnguez Conde, C., Rodrguez Valido, M., Marichal-Hernndez, J.G.: 2D-FFT implementation on FPGA for wavefront phase recovery from the CAFADIS camera. Proc. SPIE (2008)Google Scholar
  27. 27.
    Akn, B., Milder, P.A., Franchetti, F., Hoe, J.C.: Memory bandwidth efficient two-dimensional Fast Fourier Transform algorithm and implementation for large problem sizes. In: IEEE 20th International Symposium on Field-Programmable Custom Computing Machines (2012)Google Scholar

Copyright information

© Springer International Publishing AG 2018

Authors and Affiliations

  • S. Kala
    • 1
  • S. Nalesh
    • 2
  • Babita R. Jose
    • 1
  • Jimson Mathew
    • 3
  1. 1.Division of ElectronicsCochin University of Science and TechnologyKochiIndia
  2. 2.CAD LabIndian Institute of ScienceBangaloreIndia
  3. 3.Department of Computer Science and EngineeringIndian Institute of Technology PatnaPatnaIndia

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