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FDSOI Technology, Advantages for Analog/RF and Mixed-Signal Designs

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Hybrid ADCs, Smart Sensors for the IoT, and Sub-1V & Advanced Node Analog Circuit Design

Abstract

Fully depleted silicon on insulator (FDSOI) is one of the technology alternatives that permits today to follow CMOS More Moore law for the 28 nm node and beyond, while still dealing with fully planar transistors. A large number of publications have presented over the last years the benefits of this technology for energy-efficient integration of digital signal processing cores. This paper will focus on the benefits of FDSOI technology for analog/RF/millimeter-wave and high-speed mixed-signal circuits, by taking full advantage of ultra-wide voltage range body biasing tuning. For each category of circuits (analog/RF and mmW), concrete design examples are given in order to highlight the main design features specific to FDSOI.

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References

  1. Planes, N., Weber, O., Barral, V., Haendler, S., Noblet, D., Croain, D., Bocat, M., Sassoulas, P., Federspiel, X., Cros, A., Bajolet, A., Richard, E., Dumont, B., Perreau, P., Petit, D., Golanski, D., Fenouillet-Beranger, C., Guillot, N., Rafik, M., Huard, V., Puget, S., Montagner, X., Jaud, M.-A., Rozeau, O., Saxod, O., Wacquant, F., Monsieur, F., Barge, D., Pinzelli, L., Mellier, M., Boeuf, F., Arnaud, F., Haond, M.: 28 nm FD-SOI technology platform for high-speed low-voltage digital applications. In: Proceedings of Symposium VLSI Technology (VLSIT), pp. 133–134 (2012)

    Google Scholar 

  2. Arnaud, F., Planes, N., Weber, O., Barral, V., Haendler, S., Flatresse, P., Nyer, F.: Switching energy efficiency optimization for advanced CPU thanks to UTBB technology. In: IEEE International Electron Devices Meeting (IEDM) Dig., pp. 3.2.1–3.2.4 (2012)

    Google Scholar 

  3. Jacquet, D., Hasbani, F., Flatresse, P., Wilson, R., Arnaud, F., Cesana, G., Di Gilio, T., Lecocq, C., Roy, T., Chhabra, A., Grover, C., Minez, O., Uginet, J., Durieu, G., Adobati, C., Casalotto, D., Nyer, F., Menut, P., Cathelin, A., Vongsavady, I., Magarshack, P.: A 3 GHz Dual Core Processor ARM Cortex TM -A9 in 28 nm UTBB FD-SOI CMOS With Ultra-Wide Voltage Range and Energy Efficiency Optimization. IEEE J. Solid-State Circuits. 49(4), (2014)

    Google Scholar 

  4. Kumar, A., Debnath, C., Narayan Singh, P., Bhatia, V., Chaudhary, S., Jain, V., Le Tual, S., Malik, R.: A 0.065mm2 19.8mW single channel calibration-free 12b 600MS/s ADC in 28nm UTBB FDSOI using FBB. In: ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, pp. 165–168 (2016)

    Google Scholar 

  5. Nauta, B.: A CMOS transconductance-C filter technique for very high frequencies. IEEE J. Solid-State Circuits. 27(2), 142–153 (1992)

    Article  Google Scholar 

  6. Lechevallier, J., Struiksma, R., Sherry, H., Cathelin, A., Klumperink, E., Nauta, B.: A forward-body-bias tuned 450 MHz Gm-C 3rd-order low-pass filter in 28nm UTBB FD-SOI with >1dBVp IIP3 over a 0.7-to-1V supply. In: 2015 IEEE International Solid-State Circuits Conference – (ISSCC) Digest of Technical Papers, pp. 1–3 (2015)

    Google Scholar 

  7. Houfaf, F. et al.: A 65nm CMOS 1-to-10GHz Tunable Continuous-Time Lowpass Filter for High-Data-Rate Communications. In: IEEE ISSCC Digest of Techical Papers, pp. 362–364 (2012)

    Google Scholar 

  8. Kwon, K., et al.: A 50–300-MHz highly linear and low-noise CMOS gm-C filter adopting multiple gated transistors for digital TV tuner ICs. IEEE Trans. Microwave Theory Techn. 57(2), 306–313 (2009)

    Article  Google Scholar 

  9. Larie, A., Kerhervé, E., Martineau, B., Vogt, L., Belot, L.: A 60GHz 28nm UTBB FD-SOI CMOS reconfigurable power amplifier with 21% PAE, 18.2dBm P1dB and 74mW PDC. In: 2015 IEEE International Solid-State Circuits Conference – (ISSCC) Digest of Technical Papers, pp. 1–3 (2015)

    Google Scholar 

  10. Danilovic, D., Milovanovic, V., Cathelin, A., Vladimirescu, A., Nikolic, B.: Low-power inductorless RF receiver front-end with IIP2 calibration through body bias control in 28 nm UTBB FDSOI. In: 2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), pp. 87–90 (2016)

    Google Scholar 

  11. de Streel, G., Stas, F., Gurné, T., Durant, F., Frenkel, C., Cathelin, A., Bol, D.: Sleep Talker: A ULV 802.15.4a IR-UWB Transmitter SoC in 28-nm FDSOI Achieving 14 pJ/b at 27 Mb/s With Channel Selection Based on Adaptive FBB and Digitally Programmable Pulse Shaping. IEEE J. Solid-State Circuits. PP(99), 1–15 (2017)

    Google Scholar 

  12. Sourikopoulos, I., Frappé, A., Cathelin, A., Clavier, L., Kaiser, A.: A digital delay line with coarse/fine tuning through gate/body biasing in 28nm FDSOI. In: ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, pp. 145–148 (2016)

    Google Scholar 

  13. Fanori, L., Mahmoud, A., Mattsson, T., Caputa, P., Rämö, S., Andreani, P.: A 2.8-to-5.8 GHz harmonic VCO in a 28 nm UTBB FD-SOI CMOS process. In: 2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), pp. 195–198 (2015)

    Google Scholar 

  14. Lahiri, A., Gupta, N.: A 0.0175 mm2 600 μW 32kHz input 307 MHz output PLL with 190 psrms jitter in 28 nm FD-SOI. In: ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, pp. 339–342 (2016)

    Google Scholar 

  15. Le Tual, S., Narayan Singh, P., Curis, C., Dautriche, P.: A 20 GHz-BW 6b 10GS/s 32 mW time-interleaved SAR ADC with Master T&H in 28 nm UTBB FDSOI technology. In: 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), pp. 382–383 (2014)

    Google Scholar 

  16. Zimmer, B., Lee, Y., Puggelli, A., Kwak, J., Jevtić, R., Keller, B., Bailey, S., Blagojević, M., Chiu, P.-F., Le, H.-P., Chen, P.-H., Sutardja, N., Avizienis, R., Waterman, A., Richards, B., Flatresse, P., Alon, E., Asanović, K., Nikolić, B.: A RISC-V vector processor with simultaneous-switching switched-capacitor DC–DC converters in 28 nm FDSOI. IEEE J. Solid-State Circuits. 51(4), 930–942 (2016)

    Article  Google Scholar 

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Authors and Affiliations

  1. STMicroelectronics, Crolles, France

    Andreia Cathelin

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  1. Andreia Cathelin
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Correspondence to Andreia Cathelin .

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Editors and Affiliations

  1. Department of Electrical Engineering, Eindhoven University of Technology, Eindhoven, Noord-Brabant, The Netherlands

    Pieter Harpe

  2. Department of Microelectronics, Delft University of Technology, Delft, Zuid-Holland, The Netherlands

    Kofi A. A. Makinwa

  3. Department of Physics G. Occhialini, University of Milan, Milano, Italy

    Andrea Baschirotto

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Cathelin, A. (2018). FDSOI Technology, Advantages for Analog/RF and Mixed-Signal Designs. In: Harpe, P., Makinwa, K., Baschirotto, A. (eds) Hybrid ADCs, Smart Sensors for the IoT, and Sub-1V & Advanced Node Analog Circuit Design. Springer, Cham. https://doi.org/10.1007/978-3-319-61285-0_13

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  • DOI: https://doi.org/10.1007/978-3-319-61285-0_13

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  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-61284-3

  • Online ISBN: 978-3-319-61285-0

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