MC2: Multicore and Cache Analysis via Deterministic and Probabilistic Jitter Bounding

Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 10300)


In critical domains, reliable software execution is increasingly involving aspects related to the timing dimension. This is due to the advent of high-performance (complex) hardware, used to provide the rising levels of guaranteed performance needed in those domains. Caches and multicores are two of the hardware features that have the potential to significantly reduce WCET estimates, yet they pose new challenges on current-practice measurement-based timing analysis (MBTA) approaches. In this paper we propose MC2, a technique for multilevel-cache multicores that combines deterministic and probabilistic jitter-bounding approaches to reliably handle both the variability in execution time generated by caches and the contention in accessing shared hardware resources. We evaluate MC2 on a COTS quad-core LEON-based board and our initial results show how it effectively captures cache and multicore contention in pWCET estimates with respect to actual observed values.


WCET MBTA Multicore contention Probabilistic timing analysis Jitter bounding 



This work has been partially supported by the Spanish Ministry of Economy and Competitiveness (MINECO) under grant TIN2015-65316-P and the HiPEAC Network of Excellence. Jaume Abella has been partially supported by the MINECO under Ramon y Cajal postdoctoral fellowship number RYC-2013-14717. Carles Hernández is jointly funded by the MINECO and FEDER funds through grant TIN2014-60404-JIN. Authors would like to thank Pedro Benedicte for his technical feedback on the camera ready version of this article.


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© Springer International Publishing AG 2017

Authors and Affiliations

  1. 1.Barcelona Supercomputing Center (BSC)BarcelonaSpain
  2. 2.Universitat Politècnica de CatalunyaBarcelonaSpain
  3. 3.IIIA-CSICBellaterraSpain

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