Abstract
Clock domain crossing (CDC) has become an ever-increasing problem in multi-clock domain designs. One must solve issues not only at RTL level but also consider the physical timing. This chapter will start with understanding of metastability and then dive into different synchronizing techniques. It will also discuss the role of SystemVerilog Assertions in verification of CDC. We will then discuss a complete methodology.
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Mehta, A.B. (2018). Clock Domain Crossing (CDC) Verification. In: ASIC/SoC Functional Design Verification. Springer, Cham. https://doi.org/10.1007/978-3-319-59418-7_8
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DOI: https://doi.org/10.1007/978-3-319-59418-7_8
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Publisher Name: Springer, Cham
Print ISBN: 978-3-319-59417-0
Online ISBN: 978-3-319-59418-7
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