Abstract
Constrained Random Verification (CRV) is a methodology that is supported by SystemVerilog which has a built-in constraint solver. This allows you to constraint your stimulus to better target a design function, thereby allowing you to reach your coverage goal faster with accuracy. From that sense, coverage and CRV go hand in hand. You check your coverage and see where the coverage holes are. You then constrain your stimulus to target those holes and improve coverage.
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SystemVerilog_LRM_1800-2012. (n.d.). SystemVerilog LRM 1800-2012.
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Mehta, A.B. (2018). Constrained Random Verification (CRV). In: ASIC/SoC Functional Design Verification. Springer, Cham. https://doi.org/10.1007/978-3-319-59418-7_5
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DOI: https://doi.org/10.1007/978-3-319-59418-7_5
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