Abstract
Static verification is an umbrella term, and there are many different technologies that fall under it, for example, Logic Equivalence Check (LEC), Clock Domain Crossing (CDC) check, X-state verification, low-power structural checks, ESL ⇔ RTL equivalency, etc. This chapter will discuss all these topics and a lot more including state-space explosion problem, role of SystemVerilog Assertions, etc.
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Mehta, A.B. (2018). Static Verification (Formal-Based Technologies). In: ASIC/SoC Functional Design Verification. Springer, Cham. https://doi.org/10.1007/978-3-319-59418-7_10
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DOI: https://doi.org/10.1007/978-3-319-59418-7_10
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Publisher Name: Springer, Cham
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Online ISBN: 978-3-319-59418-7
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