Abstract
We consider the verification of digital systems which are incomplete in the sense that for some modules only their interfaces (i.e., the signals entering and leaving the module) are known, but not their implementations. For such designs, we study realizability (“Is it possible to implement the missing modules such that the complete design has certain properties?”) and validity (“Does a property hold no matter how the missing parts are implemented?”).
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Notes
- 1.
In the following, we denote individual signals or variables in italic font (like x, y, z) and vectors in upright bold font (like \(\mathbf {x}, \mathbf {y},\mathbf {z}\)).
- 2.
In this example we assume that the inputs of the black boxes are directly connected to the primary inputs. Thus we do not need to introduce separate vectors \(\mathbf {I}_1\) and \(\mathbf {I}_2\) for the black box inputs.
- 3.
Black boxes with a bounded amount of memory are reduced to the case of combinational black boxes by adding the memory of the black boxes to the surrounding circuit as mentioned above.
- 4.
In general the property can also check the primary inputs and outputs, but for sake of convenience, we omit details here.
- 5.
Here, we assume to have exactly one initial state; it is trivial to extend the following to sets of initial states.
- 6.
Since all types of gates can be expressed using two-input \( and _2\) gates, two-input \(or_2\) gates and inv gates, we can assume w. l. o. g. that the gates have types \( and _2\), \( or _2\) or \( inv \).
- 7.
Remember that \(\mathbf {s}^0\) is the initial state of the circuit.
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Becker, B., Scholl, C., Wimmer, R. (2018). Verification of Incomplete Designs. In: Drechsler, R. (eds) Formal System Verification. Springer, Cham. https://doi.org/10.1007/978-3-319-57685-5_2
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