Multivariate Analysis Exploiting Static Power on Nanoscale CMOS Circuits for Cryptographic Applications

  • Milena DjukanovicEmail author
  • Davide Bellizia
  • Giuseppe Scotti
  • Alessandro Trifiletti
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 10239)


Latest nanometer CMOS technology nodes have highlighted new issues in security of cryptographic hardware implementations. The constant growth of the static power consumption has led to a new class of side-channel attacks. Common attacks exploiting static power use an univariate approach to recover information from cryptographic engines. In our work, a multivariate approach based on information theoretic security metrics is presented. The temperature-dependence helps to exploit more information leakage from the hardware implementation. Starting from a univariate analysis, mutual information reveals that increasing the working temperature, the information leaked through the static power side channel is increased as well. In this work a multivariate analysis exploiting static power consumption is presented in which the temperature-domain is used to extract more information. The use of information theoretic approach allows to precisely quantify the amount of information that can be leaked from a cryptographic hardware implementation. The perceived information shows taking advantage of the use of more than one temperature, the security level can be decreased. The improvement achieved using the presented approach is demonstrated on a 40 nm CMOS implementation of the Present 80 crypto core.


Side-channel attack Static current Cryptography CMOS Power analysis attack Perceived information 


  1. 1.
    Kocher, P.C.: Timing attacks on implementations of Diffie-Hellman, RSA, DSS, and other systems. In: Koblitz, N. (ed.) CRYPTO 1996. LNCS, vol. 1109, pp. 104–113. Springer, Heidelberg (1996). doi: 10.1007/3-540-68697-5_9 Google Scholar
  2. 2.
    Roy, K., Mukhopadhyay, S., Mahmoodi-Meimand, H.: Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits. Proc. IEEE 91(2), 305–327 (2003)CrossRefGoogle Scholar
  3. 3.
    Alioto, M., Bongiovanni, S., Djukanovic, M., Scotti, G., Trifiletti, A.: Effectiveness of leakage power analysis attacks on DPA-resistant logic styles under process variations. IEEE Trans. Circuits Syst. I Regul. Papers 61(2), 429–442 (2014)CrossRefGoogle Scholar
  4. 4.
    Eisenbarth, T., Kumar, S., Paar, C., Poschmann, A., Uhsadel, L.: A survey of lightweight-cryptography implementations. IEEE Des. Test 24(6), 522–533 (2007)CrossRefGoogle Scholar
  5. 5.
    Alioto, M., Giancane, L., Scotti, G., Trifiletti, A.: Leakage power analysis attacks: well-defined procedure and first experimental results. In: 2009 International Conference on Microelectronics - ICM, pp. 46–49 (2009)Google Scholar
  6. 6.
    Alioto, M., Giancane, L., Scotti, G., Trifiletti, A.: Leakage power analysis attacks: a novel class of attacks to nanometer cryptographic circuits. IEEE Trans. Circuits Syst. I 57(2), 355–367 (2010)MathSciNetCrossRefGoogle Scholar
  7. 7.
    Brier, E., Clavier, C., Olivier, F.: Correlation power analysis with a leakage model. In: Joye, M., Quisquater, J.-J. (eds.) CHES 2004. LNCS, vol. 3156, pp. 16–29. Springer, Heidelberg (2004). doi: 10.1007/978-3-540-28632-5_2 CrossRefGoogle Scholar
  8. 8.
    Moradi, A.: Side-channel leakage through static power. In: Batina, L., Robshaw, M. (eds.) CHES 2014. LNCS, vol. 8731, pp. 562–579. Springer, Heidelberg (2014). doi: 10.1007/978-3-662-44709-3_31 Google Scholar
  9. 9.
    Pozo, S.M.D., Standaert, F., Kamel, D., Moradi, A.: Side-channel attacks from static power: when should we care? In: Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition. DATE 2015, Grenoble, pp. 145–150, 9–13 March 2015Google Scholar
  10. 10.
    Bellizia, D., Bongiovanni, S., Monsurro, P., Scotti, G., Trifiletti, A.: Univariate power analysis attacks exploiting static dissipation of nanometer CMOS VLSI circuits for cryptographic applications. IEEE Trans. Emerg. Topics Comput. PP(99), 1 (2016)CrossRefGoogle Scholar
  11. 11.
    Tiri, K., Verbauwhede, I.: A logic level design methodology for a secure DPA resistant ASIC or FPGA implementation. In: Proceedings Design, Automation and Test in Europe Conference and Exhibition, vol. 1, pp. 246–251, February 2004Google Scholar
  12. 12.
    Popp, T., Mangard, S.: Masked dual-rail pre-charge logic: DPA-resistance without routing constraints. In: Rao, J.R., Sunar, B. (eds.) CHES 2005. LNCS, vol. 3659, pp. 172–186. Springer, Heidelberg (2005). doi: 10.1007/11545262_13 CrossRefGoogle Scholar
  13. 13.
    Bellizia, D., Scotti, G., Trifiletti, A.: Implementation of the present-80 block cipher and analysis of its vulnerability to side channel attacks exploiting static power. In: 23rd International Conference Mixed Design of Integrated Circuits and Systems. MIXDES 2016, pp. 211–216, June 2016Google Scholar
  14. 14.
    Bellizia, D., Djukanovic, M., Scotti, G., Trifiletti, A.: Template attacks exploiting static power and application to CMOS lightweight crypto-hardware. Int. J. Circuit Theory Appl. 45(2), 229–241 (2016)CrossRefGoogle Scholar
  15. 15.
    Chandrakasan, A.P., Bowhill, W.J., Fox, F.: Design of High-Performance Microprocessor Circuits, 1st edn. IEEE Press, New York (2000)CrossRefGoogle Scholar
  16. 16.
    Mangard, S., Oswald, E., Popp, T.: Power Analysis Attacks: Revealing the Secrets of Smart Cards. Advances in Information Security. Springer, New York (2007)zbMATHGoogle Scholar
  17. 17.
    Mangard, S.: Hardware countermeasures against DPA – a statistical analysis of their effectiveness. In: Okamoto, T. (ed.) CT-RSA 2004. LNCS, vol. 2964, pp. 222–235. Springer, Heidelberg (2004). doi: 10.1007/978-3-540-24660-2_18 CrossRefGoogle Scholar
  18. 18.
    Tiri, K., Hwang, D., Hodjat, A., Lai, B.-C., Yang, S., Schaumont, P., Verbauwhede, I.: Prototype IC with WDDL and differential routing – DPA resistance assessment. In: Rao, J.R., Sunar, B. (eds.) CHES 2005. LNCS, vol. 3659, pp. 354–365. Springer, Heidelberg (2005). doi: 10.1007/11545262_26 CrossRefGoogle Scholar
  19. 19.
    Macé, F., Standaert, F.-X., Quisquater, J.-J.: Information theoretic evaluation of side-channel resistant logic styles. In: Paillier, P., Verbauwhede, I. (eds.) CHES 2007. LNCS, vol. 4727, pp. 427–442. Springer, Heidelberg (2007). doi: 10.1007/978-3-540-74735-2_29 CrossRefGoogle Scholar
  20. 20.
    Standaert, F.-X., Malkin, T.G., Yung, M.: A unified framework for the analysis of side-channel key recovery attacks. In: Joux, A. (ed.) EUROCRYPT 2009. LNCS, vol. 5479, pp. 443–461. Springer, Heidelberg (2009). doi: 10.1007/978-3-642-01001-9_26 CrossRefGoogle Scholar
  21. 21.
    Renauld, M., Standaert, F.-X., Veyrat-Charvillon, N., Kamel, D., Flandre, D.: A formal study of power variability issues and side-channel attacks for nanoscale devices. In: Paterson, K.G. (ed.) EUROCRYPT 2011. LNCS, vol. 6632, pp. 109–128. Springer, Heidelberg (2011). doi: 10.1007/978-3-642-20465-4_8 CrossRefGoogle Scholar
  22. 22.
    Bogdanov, A., et al.: PRESENT: an ultra-lightweight block cipher. In: Paillier, P., Verbauwhede, I. (eds.) CHES 2007. LNCS, vol. 4727, pp. 450–466. Springer, Heidelberg (2007). doi: 10.1007/978-3-540-74735-2_31 CrossRefGoogle Scholar
  23. 23.
    Bongiovanni, S., Centurelli, F., Scotti, G., Trifiletti, A.: Design and validation through a frequency-based metric of a new countermeasure to protect nanometer ics from side-channel attacks. J. Cryptogr. Eng. 5(4), 269–288 (2015)CrossRefGoogle Scholar
  24. 24.
    Rolfes, C., Poschmann, A., Leander, G., Paar, C.: Ultra-lightweight implementations for smart devices – security for 1000 gate equivalents. In: Grimaud, G., Standaert, F.-X. (eds.) CARDIS 2008. LNCS, vol. 5189, pp. 89–103. Springer, Heidelberg (2008). doi: 10.1007/978-3-540-85893-5_7 CrossRefGoogle Scholar
  25. 25.
    Knight, K.: Mathematical Statistics. Texts in Statistical Science Series. Chapman & Hall/CRC Press, Boca Raton (2000)zbMATHGoogle Scholar

Copyright information

© Springer International Publishing AG 2017

Authors and Affiliations

  • Milena Djukanovic
    • 1
    Email author
  • Davide Bellizia
    • 2
  • Giuseppe Scotti
    • 2
  • Alessandro Trifiletti
    • 2
  1. 1.Faculty of Electrical EngineeringUniversity of MontenegroPodgoricaMontenegro
  2. 2.DIETUniversità di Roma “La Sapienza”RomeItaly

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