Architecture and High Level Model
This chapter presents and explains the architecture of the designed ΣΔ modulators. First, the concept of ultra incomplete settling (UIS) is presented and is explained how it can be used to build a passive integrator, eliminating the need of a high gain amplifier. An integrator based in the UIS concept is studied in terms of transfer function and thermal noise. The block diagram of the modulator using the passive integrator is explained in terms of signal and noise transfer functions. The proposed architecture is presented and the high level models, for a second order and for a third order MASH modulator, are explained. From these, the optimization of the modulator’s parameters is described and its results presented. In the end, a technique to reduce the size of the capacitors is proposed, involving the use of a monostable circuit to reduce the active time of the clock phases.
KeywordsPassive integrator Ultra incomplete settling High level model Optimization Genetic algorithm Monostable circuit
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