A Framework for High Level Simulation and Optimization of Coarse-Grained Reconfigurable Architectures

  • Muhammad Adeel PashaEmail author
  • Umer Farooq
  • Muhammad Ali
  • Bilal Siddiqui
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 10216)


High-level simulation tools are used for optimization and design space exploration of digital circuits for a target Field Programmable Gate Array (FPGA) or Application Specific Integrated Circuit (ASIC) implementation. Compared to ASICs, FPGAs are slower and less power-efficient, but they are programmable, flexible and offer faster prototyping. One reason for the slow performance in FPGA is their finer granularity as they operate at bit-level. The possible solution is Coarse Grained Reconfigurable Architectures (CGRAs) that work at word-level. There already exists a myriad of CGRAs based on their architectural parameters. However, the CGRA research lacks in design automation since high-level simulation and optimization tools targeted at CGRAs are nearly non-existent. In this paper, we propose a high-level simulation and optimization framework for mesh-based homogeneous CGRAs. As expected, the results show that auto-generated homogeneous CGRAs consume 54% more resources when compared with academic FPGAs while providing around 63.3% faster mapping time.


Field Programmable Gate Array Application Specific Integrate Circuit Data Flow Graph Logic Area Reconfigurable Architecture 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


  1. 1.
    Hauser, J.R., Wawrzynek, J.: Garp: a MIPS processor with a reconfigurable coprocessor. In: Proceedings the 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, pp. 12–21, April 1997Google Scholar
  2. 2.
    Lee, G., Choi, K., Dutt, N.D.: Mapping multi-domain applications onto coarse-grained reconfigurable architectures. IEEE Trans. Comput. Aided Des. Integr. Circ. Syst. 30(5), 637–650 (2011)CrossRefGoogle Scholar
  3. 3.
    Peyret, T., Corre, G., Thevenin, M., Martin, K., Coussy, P.: An automated design approach to map applications on CGRAs. In: Proceedings of the 24th Edition of the Great Lakes Symposium on VLSI, ser. GLSVLSI 2014, pp. 229–230. ACM, New York (2014)Google Scholar
  4. 4.
    Baumgarte, V., Ehlers, G., May, F., Nückel, A., Vorbach, M., Weinhardt, M.: PACT XPP - a self-reconfigurable data processing architecture. J. Supercomput. 26(2), 167–184 (2003)CrossRefzbMATHGoogle Scholar
  5. 5.
    Goldstein, S.C., Schmit, H., Moe, M., Budiu, M., Cadambi, S., Taylor, R.R., Laufer, R.: PipeRench: a coprocessor for streaming multimedia acceleration. In: Proceedings of the 26th IEEE ISCA, pp. 28–39 (1999)Google Scholar
  6. 6.
    Guthaus, M.R., Ringenberg, J.S., Ernst, D., Austin, T.M., Mudge, T., Brown, R.B.: MiBench: a free, commercially representative embedded benchmark suite. In: IEEE International Workshop on Workload Characterization (WWC-4), pp. 3–14, December 2001Google Scholar
  7. 7.
    L’Hours, L.: Generating efficient custom FPGA soft-cores for control-dominated applications. In: Proceedings of the 16th IEEE ASAP, pp. 127–133 (2005)Google Scholar
  8. 8.
    Pasha, M.A., Farooq, U., Siddiqui, M.B.: A design-flow for high-level synthesis and resource estimation of reconfigurable architectures. In: 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS), Naples, Italy, pp. 1–6. IEEE (2015)Google Scholar
  9. 9.
    Zhao, Y.C.W.: New generation of predictive technology model for sub-45nm early design exploration. IEEE Trans. Electron Devices 53(11), 2816–2823 (2006)CrossRefGoogle Scholar
  10. 10.
    Zhang, C., Lenart, T., Svensson, H., Öwall, V.: Design of coarse-grained dynamically reconfigurable architecture for DSP applications. In: International Conference on Reconfigurable Computing and FPGAs, pp. 338–343 (2009)Google Scholar

Copyright information

© Springer International Publishing AG 2017

Authors and Affiliations

  • Muhammad Adeel Pasha
    • 1
    Email author
  • Umer Farooq
    • 2
  • Muhammad Ali
    • 1
  • Bilal Siddiqui
    • 3
  1. 1.Department of Electrical EngineeringSBASSE, LUMSLahorePakistan
  2. 2.LiP6, Sorbonne UniversitésParisFrance
  3. 3.Department of Electrical and Computer EngineeringPurdue UniversityWest LafayetteUSA

Personalised recommendations