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Reasoning About Temporal Faults Using an Activation Logic

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Book cover Quality Software Through Reuse and Integration (FMI 2016, IRI 2016 2016)

Part of the book series: Advances in Intelligent Systems and Computing ((AISC,volume 561))

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Abstract

Faults modelling is essential to anticipate failures in critical systems. Traditionally, Static Fault Trees (SFTs) are employed to this end, but Temporal and Dynamic Fault Trees (TFTs and DFTs) are gaining evidence due to their enriched power to model and detect intricate propagation of faults that lead to a failure. SFTs structure can be abstracted to Boolean expressions. An algebra with an operator to express order is needed to abstract TFT and DFT structures. These expressions for SFT, TFT, and DFT are called structure expressions.

Architectural modelling languages, such as Architecture and Analysis Design Language (AADL), have been used to model components and systems relations, including modelling of faults, errors, failures, and fault propagation. AADL tools can perform Static Fault Tree Analysis, for the faults modelled using AADL’s Error Model Annex.

In previous work, we showed an Algebra of Temporal Faults to analyse the order of occurrence of faults extending Boolean algebra to perform analysis for Temporal and Dynamic fault trees. In this work, we show a parametrized logic to express nominal and erroneous behaviours, including faults modelling, provided an algebra and a set of operational modes. We show how to use this logic together with the Algebra of Temporal Faults to analyse the occurrence of faults as well as their order and propagation. The logic created in this work is intended to help analysts to consider all possible situations in complex expressions with order-related operators, avoiding to miss some subtle (but relevant) combination.

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Notes

  1. 1.

    Whether a top event indeed causes a catastrophic or major failure is out of the scope of this paper; we consider that, if it is possible that such failure occurs, then it will.

  2. 2.

    Pandora stands for: P-AND-ORA, which translates to Priority AND, Time.

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Acknowledgements

We would like to thank Alexander Romanovsky, Zoe Andrews and Richard Payne for all discussions about fault modelling and dependability. This work was funded by CNPq, grants 476821/2011-8, 442859/2014-7, and 246956/2012-7, and by FACEPE grant IBPG-0408-1.03/11. This work was partially supported by the National Institute of Science and Technology for Software Engineering (INES, http://www.ines.org.br), funded by CNPq and FACEPE, grants 573964/2008-4 and APQ-1037-1.03/08.

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Authors and Affiliations

  1. Cidade Universitária, Av. Jornalista Anibal Fernandes, s/n, Recife, PE, 50740-560, Brazil

    André Didier & Alexandre Mota

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  1. André Didier
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  2. Alexandre Mota
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Correspondence to André Didier .

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Editors and Affiliations

  1. SPAWAR Systems Center Pacific, San Diego, California, USA

    Stuart H. Rubin

  2. Laboratoire de Communication dans les Systèmes Informatiques, Ecole nationale Supérieure d’Informatique, Algiers, Algeria

    Thouraya Bouabana-Tebibel

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Didier, A., Mota, A. (2018). Reasoning About Temporal Faults Using an Activation Logic. In: Rubin, S., Bouabana-Tebibel, T. (eds) Quality Software Through Reuse and Integration. FMI IRI 2016 2016 2016. Advances in Intelligent Systems and Computing, vol 561. Springer, Cham. https://doi.org/10.1007/978-3-319-56157-8_13

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  • DOI: https://doi.org/10.1007/978-3-319-56157-8_13

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