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Split-Gate Floating Poly SuperFlash® Memory Technology, Design, and Reliability

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Book cover Embedded Flash Memory for Embedded Systems: Technology, Design for Sub-systems, and Innovations

Part of the book series: Integrated Circuits and Systems ((ICIR))

Abstract

Split-gate embedded flash memory technology has been around for a couple of decades and has become a de facto standard for embedded products such as microcontrollers and smart cards. The majority of the large microcontroller and smartcard chip-makers and a series of fabless companies are now using some form of a split-gate embedded flash-memory technology because of its advantages in power, performance, and cost compared with traditional EEPROM or stacked-gate solutions. This chapter covers the fundamentals of split-gate embedded flash memories with an emphasis on SST’s widely adopted SuperFlash® memory technology as an example to demonstrate the benefits of a split-gate embedded flash-memory technologies. The fundamentals of SuperFlash technology, design, reliability, and scalability are discussed in detail in various sections, which would provide a detailed understanding of a split-gate, embedded flash-memory technology.

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References

  1. http://voyager.jpl.nasa.gov/science/neptune.html

  2. F. Masuoka et. al. A new Flash EEPROM cell using triple polysilicon technology, IEEE Technical Digest IEDM (1984)

    Google Scholar 

  3. Embedded Flash Memories for Nano-Scale VLSIs, chapter 6, Springer, Berlin

    Google Scholar 

  4. http://www.eetimes.com/document.asp?doc_id=1153458

  5. http://ww1.microchip.com/downloads/pr_archive/en/en546947.pdf

  6. B. Yeh, Single transistor non-volatile electrically alterable semiconductor memory device, U.S. Patent 5,029,130, 2 July 1991

    Google Scholar 

  7. S. Kianian, A. Levi, D. Lee, Y.-W. Hu, VLSI Symposium. Tech. Dig. 6A, 71–72 (1994)

    Google Scholar 

  8. D. Lee, Self aligned method of forming a semiconductor memory array of floating gate memory cells and a memory array made thereby, U.S. Patent 6,329,685, 11 Dec 2001

    Google Scholar 

  9. V. Markov, X. Liu, A. Kotov, A. Levi, T. Dang, and Y. Tkachev., in NVMTS (2003), p. 23

    Google Scholar 

  10. L.Q. Luo, Y.T. Chow, X.S. Cai, F. Zhang, Z.Q. Teo, D.X. Wang, K.Y. Lim, B.B. Zhou, J.Q. Liu, A. Yeo, T.L. Chang, Y.J. Kong, C.W. Yap, S. Lup, R. Long, J.B. Tan, D. Shum, N. Do, J.H. Kim, P. Ghazavi, V. Tiwari, in IEEE IMW (2015), pp. 165–169

    Google Scholar 

  11. Y. Tkachev, X. Liu, A. Kotov, V. Markov, A. Levi, in NVMTS (2004), pp. 45–50

    Google Scholar 

  12. N. Do, in IEEE ICICDT (2016), pp. 1–4

    Google Scholar 

  13. M. Kamiya, Y. Kojima, Y. Kato, K. Tanaka, Y. Hayashi, in IEEE IEDM (1982), pp. 741–744

    Google Scholar 

  14. A. T. Wu, T. Y. Chan, P.K. Ko, C. Hu, in IEEE IEDM (1986), pp. 584–587

    Google Scholar 

  15. H.C. Sung, F.L. Tan, T.H. Hsu, Y.C. Kao, Y.T. Lin, C.S. Wang., in IEEE Electron Device Letters, vol. 26, no. 3 (2005), pp. 194–196

    Google Scholar 

  16. Y. Dong, W. Kong, N. Do, S. L. Wang, G. Lee, in Solid-State Electronics, vol. 54 (2010), pp. 579–581

    Google Scholar 

  17. Y. Dong, W. Kong, N. Do, S. L. Wang, G. Lee, J. Semiconductors 31 (2010)

    Google Scholar 

  18. X. Liu, V. Markov, A. Kotov, T. Dang, A. Levi, in IEEE ICSSCIT (2006)

    Google Scholar 

  19. A. Kotov, A. Levi, Y. Tkachev, and V. Markov, in IEEE NVMTS, 2002

    Google Scholar 

  20. Y. Tkachev, in IEEE ICMTS (2016), pp. 110–115

    Google Scholar 

  21. H. Om’mani, M. Tadayoni, N. Thota, I. Yue, N. Do, in IEEE ICMTS (2013), pp. 192–194

    Google Scholar 

  22. Y. Tkachev, X. Liu, A. Kotov, in IEEE Transactions on Electron Devices, vol. 59, no. 1 (2012), pp. 5–11

    Google Scholar 

  23. N. Do, in IEEE IMW (2016), pp. 8–11

    Google Scholar 

  24. J. Van Houdt, P. Heremans, L. Deferm, G. Groeseneken, and H. Maes, in IEEE Transactions on Electron Devices, vol. 39 (1992), pp. 1150–1156

    Google Scholar 

  25. A. Kotov, Leading Edge Embedded Non Volatile Memories (2015)

    Google Scholar 

  26. V. Markov, K. Korablev, A. Kotov, X. Liu, Y. B. Jia, T. N. Dang, A. Levi, in IIRW Final Report (2007), pp. 43–47

    Google Scholar 

  27. V. Markov, A. Kotov, IEEE Trans. on Device and Materials Reliability, vol. 14, no. 2 (2014) pp. 672–680

    Google Scholar 

  28. V. Markov, J. Kim, A. Kotov, in Proceedings of the IEEE IMW (2016), pp. 21–24

    Google Scholar 

  29. A. Kotov, in MRS 2015 Fall Meeting, Symposium KK: Materials and Technology for Non-Volatile Memories (2015)

    Google Scholar 

  30. Y.K Lee, B. Seo, T-K Yu, B. Lee, E. Kim, C. Jeon, W. Park, Y. Kim, D. Lee, H. Lee, S. Cho, in IEEE IMW (2014), pp. 75–78

    Google Scholar 

  31. L.Q. Luo, Z.Q. Teo, Y.J. Kong, F.X. Deng, J.Q. Liu, F. Zhang, X.S. Cai, K.Y. Lim, P. Khoo, S.M. Jung, S.Y. Siah, D. Shum, C.M. Wang, J.C. Xing, G.Y. Liu, L. Tee, S.M. Lemke, P. Ghazavi, X. Liu, N. Do, in IEEE IMW (2016), pp. 149–152

    Google Scholar 

  32. T. Kono, T. Ito, T. Tsuruda, T. Nishiyama, T. Nagasawa, T. Ogawa, Y. Kawashima, H. Hidaka, T. Yamauchi, in IEEE ISSCC (2013), pp. 212–214

    Google Scholar 

  33. Y. Taito, M. Nakano, H. Okimoto, D. Odaka, T. Ito, T. Kono, K. Noguchi, H. Hidaka, T. Yamauchi, in IEEE ISSCC (2015), pp. 132–134

    Google Scholar 

  34. D. Shum, J.R. Power, R. Ullmann, E. Suryaputra, K. Ho, J. Hsiao, C.H. Tan, W. Langheinrich, C. Bukethal, V. Pissors, G. Tempel, M. Rohrich, A. Gratz, A. Iserhagen, E.O. Andersen, S. Paprotta, W. Dickenscheid, R. Strenz, R. Duschl, T. Kern, C.T. Hsieh, in IEEE IMW (2012), pp. 139–142

    Google Scholar 

  35. S.T. Kang, B. Winstead, J. Yater, M. Suhail, G. Zhang, C.-M. Hong, H. Gasquet, D. Kolar, J. Shen, B. Min, K. Loiko, A. Hardell, E. Lepore, R. Parks, R. Syzdek, S. Williams, W. Malloch, G. Chindalore, Y. Chen, Y. Shao, L. Huajun, L. Louis, S. Chaw, in IEEE IMW (2012), pp. 131–134

    Google Scholar 

  36. G. Torrente, X. Federspiel, D. Rideau, F. Monsieur, C. Tavernier, J. Coignus, D. Roy, G. Ghibaudo, in IEEE IRPS (2016), pp. 5A-4

    Google Scholar 

  37. A. Baiano, M.V. Duuren, E.V. D. Vegt, B. Schippers, R. Beurze, D.T. Mofrad, H.V. Zwol, Y. Chen, J. Chiang, H. Lokker, K.V. Dijk, J. Verbree, Y.N. Chen, J. Garbe, R. Verhaar, D. Dormans, in IEEE IMW (2015), pp. 173–176

    Google Scholar 

  38. K. Ramkumar, I. Kouznesov, V. Prabhakar, K. Shakeri, X. Yu, Y. Yang, L. Hinh, S. Lee, S. Samanta, H. M. Shih, S. Geha, in IEEE IMW (2013), pp. 199–202

    Google Scholar 

  39. J. Chang, in Leading Edge Embedded Non Volatile Memories (2015)

    Google Scholar 

  40. C. Su, H. Tran, M. Tadayoni, N. Do, J. Yang, Method of making embedded memory device with silicon-on-insulator substrate, U.S. patent 9,431,407, 30 Aug 2016

    Google Scholar 

  41. N. Do, in Leading Edge Embedded Non Volatile Memories (2015)

    Google Scholar 

  42. V. Tiwari, in Flash Memory Summit 2015—Driving Down the Memory Lane

    Google Scholar 

  43. D. Fan, C. Chen, P. Tuntasood, Flash memory cells with separated self-aligned select and erase gates, and process of fabrication, U.S. patent 6,747,310, 8 June 2004

    Google Scholar 

  44. H. Tran, A. Ly, H. Nguyen, T. Vu, Array and pitch of non-volatile memory cells, U.S. patent 7,839,682, 23 Nov 2010

    Google Scholar 

  45. H. Tran, S. Nguyen, H. Nguyen, Sense amplifier for low voltage high speed sensing, U.S. patent 7,616,028, 10 Nov 2009

    Google Scholar 

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Authors and Affiliations

  1. Microchip Technology Inc, Chandler, USA

    Nhan Do, Hieu Van Tran, Alex Kotov & Vipin Tiwari

Authors
  1. Nhan Do
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  2. Hieu Van Tran
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  3. Alex Kotov
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  4. Vipin Tiwari
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Corresponding author

Correspondence to Vipin Tiwari .

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Editors and Affiliations

  1. Renesas Electronics Corporation, Tokyo, Japan

    Hideto Hidaka

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Do, N., Van Tran, H., Kotov, A., Tiwari, V. (2018). Split-Gate Floating Poly SuperFlash® Memory Technology, Design, and Reliability. In: Hidaka, H. (eds) Embedded Flash Memory for Embedded Systems: Technology, Design for Sub-systems, and Innovations. Integrated Circuits and Systems. Springer, Cham. https://doi.org/10.1007/978-3-319-55306-1_5

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  • DOI: https://doi.org/10.1007/978-3-319-55306-1_5

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  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-55305-4

  • Online ISBN: 978-3-319-55306-1

  • eBook Packages: EngineeringEngineering (R0)

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