Advertisement

Dependability Solutions

  • Salvatore Pontarelli
  • Juan A. Maestro
  • Pedro Reviriego
Chapter

Abstract

This chapter presents an overview of existing dependability solutions for multicore processing systems. In the first section, the existing techniques to protect processor cores both at the hardware and software level are discussed. Then the protection of the different memories that are present in a multicore is reviewed in the second section. Finally, the protection of the interconnections is covered in the last section.

References

  1. 1.
    H. Cho, S. Mirkhani, C.-Y. Cher, J. Abraham, S. Mitra, Quantitative evaluation of soft error injection techniques for robust system design, in Proceeding of DAC’13, Austin, TX, USAGoogle Scholar
  2. 2.
    M. Ottavi, S. Pontarelli, D. Gizopoulos, C. Bolchini, M.K. Michael, L. Anghel, M. Tahoori, A. Paschalis, P. Reviriego et al., Dependable multicore architectures at nanoscale: the view from Europe. IEEE Des. Test Comput. 32(2), 17–28 (2015)CrossRefGoogle Scholar
  3. 3.
    S.K. Reinhardt, S.S. Mukherjee, Transient fault detection via simultaneous multithreading, in Proceedings of The 27th International Symposium on Computer Architecture, June 2000Google Scholar
  4. 4.
    S.S.Mukherjee, M. Kontz, S.K. Reinhardt, Detailed design and evaluation of redundant multithreading alternatives, in ISCA, 2002Google Scholar
  5. 5.
    S. Campagna, M. Hussain, M. Violante, Hypervisor-based virtual hardware for fault tolerance in COTS processors targeting space applications, in Proceedings of International Symposium on Defect Fault Tolerance VLSI System, 2010, pp. 44–51Google Scholar
  6. 6.
    D. Gizopoulos et al., Architectures for online error detection and recovery in multicore processors, in Proceedings of Design, Automation Test in Europe (DATE), 2011, pp. 533–538Google Scholar
  7. 7.
    J.T. Daly, A higher order estimate of the optimum checkpoint interval for restart dumps. Future Gener. Comput. Syst. 22(3), 303–312 (2006)CrossRefGoogle Scholar
  8. 8.
    M. Bougeret, H. Casanova, M. Rabie, Y. Robert, F. Vivien, Checkpointing strategies for parallel jobs, in Supercomputing, SC ’11 (ACM, New York, NY, USA, 2011), pp. 1–11Google Scholar
  9. 9.
    X. Ni, E. Meneses, N. Jain, L.V. Kalé, ACR: automatic checkpoint/restart for soft and hard error protection, in Proceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis, Denver, Colorado, 17–21 November 2013Google Scholar
  10. 10.
    B. Mills, R. Melhem, Shadow computing: an energy-aware fault tolerant computing model, in 2014 International Conference on Computing, Networking and Communications (ICNC), Honolulu, HI, 3–6 February 2014Google Scholar
  11. 11.
    H. Zhou, A case for fault-tolerance and performance enhancement using chip multiprocessors. IEEE Comput. Archit. Lett. 5(1), 22–25 (2006)Google Scholar
  12. 12.
    H. Zhou, Dual-core execution: building a highly scalable single-thread instruction window, in PACT’05, 2005Google Scholar
  13. 13.
    J. Gaisler, A portable and fault-tolerant microprocessor based on the SPARC v8 architecture, in Proceedings of International Conference on Dependable Systems and Networks, 2002, pp. 409–415Google Scholar
  14. 14.
    L.T. Clark, D.W. Patterson, C. Ramamurthy, K.E. Holbert, An Embedded Microprocessor Radiation Hardened by Microarchitecture and Circuits. IEEE Trans. Comput. 65(2), 382–395 (2016)MathSciNetCrossRefGoogle Scholar
  15. 15.
    T.M. Austin, DIVA: a reliable substrate for deep submicron microarchitecture design, MICRO 1999Google Scholar
  16. 16.
    A. Bouajila, T. Sommer, J. Zeppenfeld, W. Stechele, A. Herkersdorf, A Fault-Tolerant Processor Architecture, in 22nd International Conference on Architecture of Computing Systems (ARCS) (Delft, The Netherlands, 11 March 2009), pp. 1–5Google Scholar
  17. 17.
    A. Meixner, M.E. Bauer, D.J. Sorin, Argus: low-cost, comprehensive error detection in simple cores, MICRO (2007)Google Scholar
  18. 18.
    C. Weaver, J. Emer, S. Mukherjee, S.K. Reinhardt, Techniques to reduce the soft error rate of a high-performance microprocessor, in Annual International Symposium on Computer Architecture, 2004Google Scholar
  19. 19.
    G. Reis, J. Chang, N. Vachharajani, R. Rangan and D. August, SWIFT: Software implemented fault tolerance, in Proceedings of International Symposium on Code Generation Optimization, 2005, pp. 243–254Google Scholar
  20. 20.
    G.A. Reis, J. Chang, D.I. August, Automatic instruction-level software only recovery method. IEEE Micro 27(1) (2007)Google Scholar
  21. 21.
    N. Oh, P.P. Shirvani, E.J. McCluskey, Control flow checking by software signatures. IEEE Trans. Reliab. 51, 111–122 (2002)CrossRefGoogle Scholar
  22. 22.
    Z. Alkhalifa, V.S.S. Nair, N. Krishnamurthy, J.A. Abraham, Design and evaluation of system-level checks for on-line control flow error detection. IEEE Trans. Parallel Distrib. Syst 10(6), 627–641 (1999)CrossRefGoogle Scholar
  23. 23.
    O. Goloubeva, M. Rebaudengo, M.S. Reorda, M. Violante, Soft-error detection using control flow assertions, in Proceedings of 18th IEEE International Symposium Defect and Fault Tolerance in VLSI Systems, 2003, pp. 581–588Google Scholar
  24. 24.
    R. Venkatasubramanian, J.P. Hayes, B.T. Murray, Low-cost on-line fault detection using control flow assertions, in IOLTS’03: Proceedings of 12th IEEE International On-Line Testing Symposium, 2003, pp. 137–143Google Scholar
  25. 25.
    R. Vemu, J. Abraham, Ceda: control-flow error detection using assertions. IEEE Trans. on Comput 90(9), 1233–1245 (2011)MathSciNetCrossRefMATHGoogle Scholar
  26. 26.
    M. Psarakis, D. Gizopoulos, E. Sanchez, M. Sonza Reorda, Microprocessor software-based self-testing. IEEE Des Test of Comput 27(3), 4–19Google Scholar
  27. 27.
    N. Foutris, M. Psarakis, D. Gizopoulos, A. Apostolakis, X. Vera, A. Gonzalez, MT-SBST: self-test optimization in multithreaded multicore architectures, in Proceeding of IEEE Internationl Test Conference, 2010, pp. 1–10Google Scholar
  28. 28.
    J.-F. Li, J.-C. Yeh, R.-F. Huang, C.-W. Wu, A built-in self-repair design for RAMs with 2-D redundancies. IEEE Trans. Very Large Scale Integr. Syst. 13(6), 742–745 (2005)CrossRefGoogle Scholar
  29. 29.
    C.L. Chen, M.Y. Hsiao, Error-correcting codes for semiconductor memory applications: a state-of-the-art review. IBM J. Res. Dev. 28(2), 124–134 (1984)CrossRefGoogle Scholar
  30. 30.
    S. Lin, D.J. Costello, error control coding, 2nd edn. (Englewood Cliffs, New Jersey, Prentice-Hall, 2004)MATHGoogle Scholar
  31. 31.
    J.J. Metzner, Convolutionally encoded memory protection. IEEE Trans. Comput. 31(6), 547–551 (1983)Google Scholar
  32. 32.
    M.Y. Hsiao, A class of optimal minimum odd-weight column SEC-DED codes. IBM J. Res. Dev. 14(4), 395–401 (1970)CrossRefGoogle Scholar
  33. 33.
    E. Ibe, H. Taniguchi, Y. Yahagi, K. Shimbo, T. Toba, Impact of scaling on neutron-induced soft error rate in SRAMs from a 250 nm to a 22 nm design rule. IEEE Trans. Electron Devices 57(7), 1527–1538 (2010)CrossRefGoogle Scholar
  34. 34.
    A. Dutta, N.A. Touba, Multiple bit upset tolerant memory using a selective cycle avoidance based SEC-DED-DAEC code, in 25th IEEE VLSI Test Symposium, 2007, pp. 349–354Google Scholar
  35. 35.
    L.J. Saiz-Adalid, P. Reviriego, P. Gil, S. Pontarelli, J.A. Maestro, MCU tolerance in SRAMs through low redundancy triple adjacent error correction. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 23(10), 2332–2336 (2015)Google Scholar
  36. 36.
    M.A. Bajura et al., Models and algorithmic limits for an ECC-based approach to hardening sub-100-nm SRAMs. IEEE Trans. Nucl. Sci. 54(4), 935–945 (2007)CrossRefGoogle Scholar
  37. 37.
    S. Mukherjee, Architecture design for soft errors (Morgan Kaufmann, 2008)Google Scholar
  38. 38.
    E. Fetzer, D. Dahle, C. Little, K. Safford, The parity protected, multithreaded register files on the 90-nm Itanium microprocessor. IEEE J. Solid-State Circuits 41(1), 246–255 (2006)CrossRefGoogle Scholar
  39. 39.
    P. Reviriego, S. Pontarelli, J.A. Maestro, M. Ottavi, Low-cost single error correction multiple adjacent error correction codes. IET Electron. Lett. 48(23), 1470–1472 (2012)CrossRefMATHGoogle Scholar
  40. 40.
    P. Reviriego, S. Pontarelli, J.A. Maestro, M. Ottavi, A method to construct low delay Single Error Correction (SEC) codes for protecting data bits only. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(3), 479–483 (2013)CrossRefGoogle Scholar
  41. 41.
    R. Naseer, R. Bhatt, J. Draper, Analysis of soft error mitigation techniques for register files in IBM Cu-08 90 nm technology, in Proceeding of IEEE International Midwest Symposium Circuits and Systems, 2006, pp. 515–519Google Scholar
  42. 42.
    O. Ergin, O. Unsal, X. Vera, A. González, Exploiting narrow values for soft error tolerance. IEEE Comput. Archit. Lett. 5 (2006)Google Scholar
  43. 43.
    I.B. Karsli, P. Reviriego, M.F. Balli, O. Ergin, J.A. Maestro, Enhanced duplication: a technique to correct soft errors in narrow values, IEEE Comput. Archit. Lett. 12(1), 13–16 (2013)Google Scholar
  44. 44.
    P. Montesinos et al., Using register lifetime predictions to protect register files against soft errors, in Proceeding of Dependable Systems and Networks, 2007, pp. 286–296Google Scholar
  45. 45.
    J. Lee, A. Shrivastava, Static analysis to mitigate soft errors in register files, in Proceeding of Design, Automation and Test in Europe (DATE), April 2009, pp. 1367–1372Google Scholar
  46. 46.
    J. Lee, A. Shrivastava, A compiler-microarchitecture hybrid approach to soft error reduction for register files. IEEE Trans. Comput. Aided Des. Integr. Circuits and Syst. 29(7), 1018–1027 (2010)CrossRefGoogle Scholar
  47. 47.
    M. Fazeli, A. Namazi, S.G. Miremadi, An energy efficient circuit level technique to protect register file from MBUs and SETs in embedded processors, in Proceeding of Dependable Systems and Networks, 2009, pp. 195–204Google Scholar
  48. 48.
    L.T. Clark, D.W. Patterson, C. Ramamurthy, K.E. Holbert, An embedded microprocessor radiation hardened by microarchitecture and circuits. IEEE Trans. Comput. 65(2), 382–395 (2016)MathSciNetCrossRefGoogle Scholar
  49. 49.
    J. Kim, N. Hardavellas, K. Mai, B. Falsafi, J.C. Hoe, Multi-bit error tolerant caches using two-dimensional error coding, in Proceeding of the 40th IEEE/ACM International Symposium on Microarchitecture (MICRO), December 2007Google Scholar
  50. 50.
    W. Zhang, S. Gurumurthi, M. Kandemir, A. Sivasubramaniam, ICR: In-cache replication for enhancing data cache reliability, in Proceeding of the International Conference on Dependable Systems and Networks (DSN), June 2003Google Scholar
  51. 51.
    M.Y. Hsiao, D.C. Bossen, R.T. Chien, Orthogonal Latin square codes. IBM J. Res. Dev. 14(4), 390–394 (1970)MathSciNetCrossRefMATHGoogle Scholar
  52. 52.
    A.R. Alameldeen, Z. Chishti, C. Wilkerson, W. Wu, S.-L. Lu, Adaptive cache design to enable reliable low-voltage operation. IEEE Trans. Comput. 60(1), 50–63 (2011)MathSciNetCrossRefGoogle Scholar
  53. 53.
    D. H. Yoon, M. Erez, Memory mapped ECC: low-cost error protection for last level caches, in Proceeding of the 36th Annual International Symposium on Computer Architecture (ISCA), 2009Google Scholar
  54. 54.
    P. Reviriego, C. Argyrides, J.A. Maestro, Efficient error detection in double error correction BCH codes for memory applications. Microelectron. Reliab. 52(7), 1528–1530 (2012)CrossRefGoogle Scholar
  55. 55.
    J. Kim, S. Kim, Y. Lee, SimTag: exploiting tag bits similarity to improve the reliability of the data caches, in Proceeding Design Automation and Test in Europe, 2010Google Scholar
  56. 56.
    S. Wang, J. Hu, S.G. Ziavras, Replicating tag entries for reliability enhancement in cache tag arrays. IEEE Trans. Very Large Scale Integr. Syst. 20(4), 643–654 (2012)CrossRefGoogle Scholar
  57. 57.
    P. Reviriego, S. Pontarelli, M. Ottavi, J.A. Maestro, FastTag: a technique to protect cache tags against soft errors. IEEE Trans. Device Mater. Reliab. 14(3), 935–937 (2014)CrossRefGoogle Scholar
  58. 58.
    P. Reviriego, S.S. Liu, A. Sánchez-Macián, L.Y. Xiao, J.A. Maestro, Unequal error protection codes derived from SEC-DED codes, IET Electron. Lett. (2016) (in press)Google Scholar
  59. 59.
    V. Sridharan, D. Liberty, A study of DRAM failures in the field, in Proceeding of the International Conference on High Performance Computing, Networking, Storage and Analysis, 2102Google Scholar
  60. 60.
    B. Schroeder, E. Pinheiro, W-D. Weber, DRAM errors in the wild: a large-scale field study, in Proceeding of ACM SIGMETRICS, 2009Google Scholar
  61. 61.
    H. Schmidt, M. Hermann, K. Grürmann, F. Gliem, V. Ferlet-Cavrois, Radiation hard memory. Radiation testing of candidate memory devices for Laplace mission, CNES/ESA Radiation effects final presentation days, March 2015Google Scholar
  62. 62.
    International Business Machines Corporation (IBM) “Chipkill Memory,” http://www-05.ibm.com/hu/termekismertetok/xseries/dn/chipkill.pdf, Technical Report, 2012
  63. 63.
    X. Jian, H. Duwe, J. Sartori, V. Sridharan, R. Kumar, Low-power, low-storage-overhead chipkill correct via multi-line error correction, in Proceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis (SC), 2013Google Scholar
  64. 64.
    S. Pontarelli, G.C. Cardarilli, M. Re, A. Salsano, Error correction codes for SEU and SEFI tolerant memory systems, in 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, October 2009, pp. 425–430Google Scholar
  65. 65.
    D.H. Yoon, M. Erez, Virtualized and flexible ECC for main memory, in Proceeding of the International Symposium on Architectural Support for Programming Languages and Operating Systems, 2010Google Scholar
  66. 66.
    A.N. Udipi, N. Muralimanohar, R. Balsubramonian, A. Davis, N.P. Jouppi, LOT-ECC: localized and tiered reliability mechanisms for commodity memory systems, in Proceeding of the International Symposium on Computer Architecture, 2012Google Scholar
  67. 67.
    J. Kim, M. Sullivan, M. Erez, Bamboo ECC: strong, safe, and flexible codes for reliable computer memory, in Proceeding of the International Symposium on High Performance Computer Architecture, 2015Google Scholar
  68. 68.
    C. Weis, I. Loi, L. Benini, N. Wehn, Exploration and optimization of 3-D integrated DRAM subsystems, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.32(4) (2013)Google Scholar
  69. 69.
    A. Schoenberger, K. Hofmann, Analysis of asymmetric 3D DRAM architecture in combination with L2 cache size reduction, in Proceeding of the IEEE High Performance Computing & Simulation (HPCS), 2015Google Scholar
  70. 70.
    R Kumar, V Zyuban, D.M. Tullsen, Interconnections in multi-core architectures: understanding mechanisms, overheads and scaling, in 32nd International Symposium on Computer Architecture (ISCA’05), 2005Google Scholar
  71. 71.
    D. Bertozzi, L. Benini, G. De Micheli, Error control schemes for on-chip communication links: the energy-reliability tradeoff. IEEE Trans. Comput.-Aided Des. of Integr. Circuits and Syst. 24(6), 818–831 (2005)CrossRefGoogle Scholar
  72. 72.
    L. Benini, G. De Micheli, Networks on chips: a new SoC paradigm. IEEE Comput. 35(1), 70–78 (2002)CrossRefGoogle Scholar
  73. 73.
    S. Murali, N. Vijaykrishnan, M.J. Irwin, L. Benini, G. De Micheli, Analysis of error recovery schemes for networks on chips. IEEE Des. Test Comput. 22(5), 434–442 (2005)CrossRefGoogle Scholar
  74. 74.
    A. Ejlali, et al., Joint consideration of fault-tolerance, energy-efficiency and performance in on-chip networks, in Proceeding of Design, Automation and Test in Europe Conference and Exhibition, 2007Google Scholar
  75. 75.
    B. Fu, P. Ampadu, Error control for network-on-chip links (Springer Science & Business Media, 2011)Google Scholar
  76. 76.
    S. Lee et al., Low-power, resilient interconnection with orthogonal Latin squares. IEEE Des. Test Comput. 28(2), 30–39 (2011)CrossRefGoogle Scholar
  77. 77.
    D. Rossi, C. Metra, K.A. Nieuwland, A. Katoch, Exploiting ECC redundancy to minimize crosstalk impact. IEEE Des. & Test Comput. 22, 59–70 (2005)CrossRefGoogle Scholar
  78. 78.
    A. Ganguly, P.P. Pande, B. Belzer, Crosstalk-aware channel coding schemes for energy efficient and reliable NOC interconnects. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 17(11), 1626–1639, 2009Google Scholar
  79. 79.
    S. Sridhara, R.N. Shanbhag, Coding for reliable on-chip buses: a class of fundamental bounds and practical codes. IEEE Trans. Comput. Aided Des. Integr. Circuits and Syst. 5, 977–982 (2007)CrossRefGoogle Scholar
  80. 80.
    T. Lehtonen, P. Lijieberg J. Plosila, Analysis of forward error correction methods for nanoscale networks-on-chip, in Proceedings of the nano-net, 2007, Catania, Italy, pp. 1–5Google Scholar
  81. 81.
    B. Fu, P. Ampadu, On hamming product codes with type-II hybrid ARQ for on-chip interconnects. IEEE Trans. Circuits Syst. I, Regul. Pap. 56(9), 2042–2054 (2009)MathSciNetCrossRefGoogle Scholar
  82. 82.
    P. Ampadu, Q. Yu, B. Fu, Reliable networks-on-chip design for sustainable computing systems, in Design Technologies for Green and Sustainable Computing Systems (Springer New York), pp. 23–57Google Scholar
  83. 83.
    C. Feng, Z. Lu, A. Jantsch, M. Zhang, Z. Xing, Addressing transient and permanent faults in NoC with efficient fault-tolerant de-flection router. IEEE Trans. Very Large Scale Integr. VLSI Syst. 21(6), 1053–1066 (2013)CrossRefGoogle Scholar
  84. 84.
    S. Dumitras, R. Kerner, R. Marculescu, Towards on-chip fault-tolerant communication, in Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC’03), Kitakyushu, Japan, pp. 225–232Google Scholar
  85. 85.
    Z.J. Haas, J. Y. Halpern, L. Li Gossip-based ad hoc routing. IEEE/ACM Trans. Networking 14, 476–49, 2006Google Scholar
  86. 86.
    M. Pirretti et al., Fault tolerant algorithms for network-on-chip interconnect, in Proceeding IEEE Computer Society Annual Symposium on VLSI Emerging Trends in VLSI System Design, (ISVLSI’04), Lafayette, Louisiana, USA, 2004, pp. 46–51Google Scholar
  87. 87.
    T. Lehtonen, D. Wolpert, P. Liljeberg, J. Plosila, P. Ampadu, Self-adaptive system for addressing permanent errors in on-chip interconnects. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 18(4), 527–540 (2010)CrossRefGoogle Scholar
  88. 88.
    C. Grecu, P. Pande, A. Ivanov, R. Saleh, BIST for network-on-chip interconnect infrastructures, in Proceedings of the 24th IEEE VLSI Test Symposium, 2006Google Scholar
  89. 89.
    M. Radetzki, C Feng, X Zhao, A Jantsch, Methods for fault tolerance in networks-on-chip ACM Comput. Surv. 46(1), pp. 8:1, 8:38 (2013)Google Scholar
  90. 90.
    E. Bolotin,I. Cidon, R. Ginosar, A. Kolodny, “Routing table minimization for irregular mesh NoCs”, In proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE’07). 1–6Google Scholar
  91. 91.
    J. Flich, A. Mejia, P. Lopez, J. Duato, Region-based routing: an efficient routing mechanism to tackle unreliable hardware in network on chips, in Proceedings of the Symposium on Networks-on-Chip, (NOCS’07), 2007, pp. 183–194Google Scholar
  92. 92.
    Z. Zhang, A. Greiner, S. Taktak, A reconfigurable routing algorithm for a fault-tolerant 2D-mesh network-on-chip, in Proceedings of IEEE Design Automation Conference (DAC’08), 2008, pp. 441–446Google Scholar
  93. 93.
    C. Bobda et al., DyNoC: a dynamic infrastructure for communication in dynamically reconfigurable devices, in Proceedings of International Conference on Field Programmable Logic and Applications, (FPL08), 2008, pp. 153–158Google Scholar
  94. 94.
    M. Valinataj, S. Mohammadi, J. Plosila, P. Liljeberg, A fault-tolerant and congestion-aware routing algorithm for Networks-on-chip. DDECS 2010, 139–144 (2010)Google Scholar
  95. 95.
    M. Ebrahimi, M. Daneshtalab, J. Plosila, H. Tenhunen, MAFA: adaptive fault-tolerant routing algorithm for networks-on-chip. DSD 2012, 201–207 (2012)Google Scholar
  96. 96.
    M. Dimopoulos, et al., Fault-tolerant adaptive routing under permanent and temporary failures for many-core systems-on-chip, in Proceeding of the 9th IEEE International On-Line Testing Symposium (IOLTS13), 2013Google Scholar
  97. 97.
    W.J. Dally, C.L. Seitz, Deadlock-free message routing in multiprocessor interconnection networks. IEEE Trans. Comput. 36(5), 547–553 (1987)CrossRefMATHGoogle Scholar
  98. 98.
    K. Constantinides et al.. Bulletproof: a defect-tolerant CMP switch architecture, in Proceeding of the 12th IEEE International Symposium on High-Performance Computer Architecture, 2006, pp. 5–16Google Scholar
  99. 99.
    D. Fick, A DeOrio, J. Hu, V. Bertacco, D. Blaauw, D. Sylvester, Vicis: a reliable network for unreliable silicon, in Proceedings of the 46th ACM Annual Design Automation Conference, (DAC’09), 2009, 812–817Google Scholar
  100. 100.
    A. Kohler, M. Radetzki, Fault-tolerant architecture and deflection routing for degradable NoC switches, in Proceedings of the 3rd ACM/IEEE International Symposium on Networks-on-Chips, (NOCS’09), 2009, pp. 22–31Google Scholar

Copyright information

© Springer International Publishing AG 2018

Authors and Affiliations

  • Salvatore Pontarelli
    • 1
  • Juan A. Maestro
    • 2
  • Pedro Reviriego
    • 2
  1. 1.Consorzio Nazionale Interuniversitario Per Le Telecomunicazioni (CNIT)RomeItaly
  2. 2.Universidad Antonio de NebrijaMadridSpain

Personalised recommendations