Abstract
Peripheral circuits in the resistive synaptic arrays perform the function of neurons in neuro-inspired computing applications and are responsible for the read and write operations of resistive device arrays. The read operation in resistive arrays essentially performs the weighted sum or inner-product computation, which is the most critical operation in neural networks. On the other hand, the write operation is accountable for updating resistive synapse weights, which is the key operation for learning in neural networks. To efficiently enable these read and write operations in resistive arrays, a number of different design techniques in literature will be presented in this chapter. First the CMOS circuit implementations for the read operation and the write operation will be examined, and then recent non-CMOS circuit implementations will also be described. Advantages, trade-offs, and future design prospects of different peripheral circuit designs will be discussed.
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Kadetotad, D., Chen, PY., Cao, Y., Yu, S., Seo, Js. (2017). Peripheral Circuit Design Considerations of Neuro-inspired Architectures. In: Yu, S. (eds) Neuro-inspired Computing Using Resistive Synaptic Devices. Springer, Cham. https://doi.org/10.1007/978-3-319-54313-0_9
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