Experimental Demonstration of Firing Rate Neural Networks Based on Metal-Oxide Memristive Crossbars

  • Farnood Merrikh Bayat
  • Mirko Prezioso
  • Bhaswar Chakrabarti


Limitations of currently dominating von Neumann architectures have pushed the research toward brain-inspired solutions like neural networks to reach new levels of computing efficiency. While these highly parallelized architectures have achieved outstanding performances at software level, their hardware implementation is still a challenging problem due to the large amount of memory and arithmetic units required to store synaptic weights and implement synaptic transmission functions. One possible solution to tackle this challenging problem is to build neural networks with analog circuits and implement the functionality of synapses with the same nonvolatile memory unit that stores synaptic weights (a so-called in-memory computing). Scalability, analog behavior (multilevel programmability), speed, and power consumption are fundamental performance requirements for such memory arrays, given the huge number of synapses in state-of-the-art neural networks. Among different choices, Resistive Random Access Memories (RRAMs) are considered as one of the main candidates due to their excellent scalability and the possibility of their integration with fully mature CMOS technology. Here in this chapter, we will show the basic principles of such devices, alongside their performance as single devices and also when integrated in crossbars, all induced from experiments. We will also present the results of the first experimental realizations of single- and multi-layer neural networks with synapses implemented through crossbar arrays with detailed explanation on their in situ training. Finally, we conclude the chapter by presenting our recent progress on the 3D integration of resistive switching devices on top of CMOS-based circuitries and also by discussing the limitations of current implementations and future challenges.


Synaptic Weight Resistive Switching Chemical Mechanical Planarization Resistive Random Access Memory Memristive Device 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.



The authors would like to acknowledge useful discussion with G. Adam, K. T. Cheng, B. Hoskins, I. Kataeva, K. K. Likharev, and D. B. Strukov. The work has been supported in part by the Air Force Office of Scientific Research (AFOSR) under the MURI grant FA9550-12-1-0038, DARPA under Contract No. HR0011-13-C-0051UPSIDE via BAE Systems, and National Science Foundation grant CCF 1528205.


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Copyright information

© Springer International Publishing AG 2017

Authors and Affiliations

  • Farnood Merrikh Bayat
    • 1
  • Mirko Prezioso
    • 1
  • Bhaswar Chakrabarti
    • 1
  1. 1.Department of Electrical and Computer EngineeringUniversity of California Santa BarbaraSanta BarbaraUSA

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