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Modeling, Methodologies and Tools for Molecular and Nano-scale Communications pp 421–444Cite as

Reliable Design for Crossbar Nano-architectures

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Part of the book series: Modeling and Optimization in Science and Technologies ((MOST,volume 9))

Abstract

The conventional CMOS technology faces various challenges in the continues down-scaling. Therefore, different emerging technologies based on bottom-up and self-assembly nanofabrications are being explored to overcome these challenges. These technologies exploit different nano-materials in the regular structures such as the crossbar nano-architecture, which is a two-dimensional grid with configurable switches at the crosspoints. Exploiting nano-materials in crossbar nano-architectures offers the possibility of significantly denser circuits at reduced fabrication costs compared to the existing lithography-based manufacturing. However, in these nano-architectures atomic device sizes and poor control on the fabrication processes impairs the reliability of these circuits. In this chapter, we investigate reliability issues in crossbar nano-architectures in terms of variation and defect tolerance. We study two approaches, namely logic mapping and self-timed architecture design, to provide variation and defect tolerance. In the logic mapping approach, different configurations, a.k.a mappings, of a logic function on a crossbar nano-architecture are explored to find the configuration with the required variation and defect tolerance. Simulation results, on a set of benchmark circuits, show that the proposed logic mapping approach achieves variation tolerance more than 98% of the cases, while in 100% of the cases all defects are tolerated. The efficiency of these algorithms is independent of crossbar size. At the architecture-level, a self-timed nano-architecture is introduced to reduce the circuit vulnerability to delay variations. Compared to the synchronous counterparts, with around 50% overhead in the number of activated switches, the proposed architecture provides 100% tolerance of delay variations.

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Author information

Authors and Affiliations

  1. Qualcomm Incorporated, 5828 Pacific Center Blvd, San Diego, CA, 92121, USA

    Masoud Zamani

  2. CDNC - Chair of Dependable Nano Computing, Department of Computer Science, Karlsruhe Institute of Technology, Haid-und-Neu-Str. 7 (Technologiefabrik Karlsruhe), 76131, Karlsruhe, Germany

    Mehdi B. Tahoori

Authors
  1. Masoud Zamani
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  2. Mehdi B. Tahoori
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Correspondence to Masoud Zamani .

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Editors and Affiliations

  1. Department of Computer Science, University of Massachusetts, Boston, Massachusetts, USA

    Junichi Suzuki

  2. Graduate School of Biological Sciences, Osaka University, Osaka, Japan

    Tadashi Nakano

  3. 57006D Applied Science Building, Pennsylvania State University, State College, Pennsylvania, USA

    Michael John Moore

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Zamani, M., Tahoori, M.B. (2017). Reliable Design for Crossbar Nano-architectures. In: Suzuki, J., Nakano, T., Moore, M. (eds) Modeling, Methodologies and Tools for Molecular and Nano-scale Communications. Modeling and Optimization in Science and Technologies, vol 9. Springer, Cham. https://doi.org/10.1007/978-3-319-50688-3_18

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  • DOI: https://doi.org/10.1007/978-3-319-50688-3_18

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  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-50686-9

  • Online ISBN: 978-3-319-50688-3

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