Abstract
On one hand, traditionally, secure systems rely on hardware to store the keys for cryptographic protocols. Such an approach is becoming increasingly insecure, due to hardware-intrinsic vulnerabilities. A physical unclonable function (PUF) is a security primitive that exploits inherent hardware properties to generate keys on the fly, instead of storing them. On the other hand, the integrated circuit (IC) design flow is globalized due to increase in design, fabrication, testing, and verification costs. While globalization has provided cost benefits and reduced the time-to-market, it has introduced several attacks such as piracy, malicious modifications, and counterfeiting. To thwart these attacks, researchers have developed techniques that modify the designs and include additional components into the design. Such techniques are collectively called intellectual property (IP) protection techniques. In this chapter, we describe two classes of hardware security techniques: PUFs and IP protection techniques.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Notes
- 1.
- 2.
X refers to a don’t care value. It can be freely set to either 1 or 0.
- 3.
Two pins are compatible if one pin is the output of a gate or an input port, and the other pin is an input of a gate or an output port.
References
Kocher, P., Jaffe, J., Jun, B.: Differential power analysis. Advances in cryptology (CRYPTO 99). Lect. Notes Comput. Sci. 1666, 388–397 (1999)
SEMI. Innovation is at risk as semiconductor equipment and materials industry loses up to $4 billion annually due to IP infringement (2008). www.semi.org/en/Press/P043775
Herder, C., Yu, M.-D., Koushanfar, F., Devadas, S.: Physical unclonable functions and applications: a tutorial. Proc. IEEE 102(8), 1126–1141 (2014)
Guin, Ujjwal, DiMase, Daniel, Tehranipoor, Mohammad: Counterfeit integrated circuits: detection, avoidance, and the challenges ahead. J. Electron. Test. 30(1), 9–23 (2007)
Rostami, M., Koushanfar, F., Karri, R.: A primer on hardware security: models, methods, and metrics. P. IEEE 102(8), 1283–1295 (2014)
Roy, J.A., Koushanfar, F., Markov, I.L.: EPIC: ending piracy of integrated circuits. IEEE/ACM Design, Automation and Test in Europe, pp. 1069–1074 (2008)
Roy, J.A., Koushanfar, F., Markov, I.L.: Ending piracy of integrated circuits. Computer 43(10), 30–38 (2010)
Karri, R., Rajendran, J., Rosenfeld, K., Tehranipoor, M.: Trustworthy hardware: identifying and classifying hardware Trojans. IEEE Comput. 43(10), 39–46
Top 5 Most Counterfeited Parts Represent a $ 169 Billion Potential Challenge for Global Semiconductor Market. http://press.ihs.com/press-release/design-supply-chain/top-5-most-counterfeited-parts-represent-169-billion-potential-cha
DARPA. Defense Science Board (DSB) study on High Performance Microchip Supply (2005). www.acq.osd.mil/dsb/reports/ADA435563.pdf
Koushanfar, Farinaz, Hong, Inki, Potkonjak, Miodrag: Behavioral synthesis techniques for intellectual property protection. ACM Trans. Des. Autom. Electron. Syst. 10(3), 523–545 (2005)
Caldwell, A.E., Choi, H.-J., Kahng, A.B., Mantik, S., Potkonjak, M., Qu, G., Wong, J.L.: Effective iterative techniques for fingerprinting design IP. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 23(2), 208–215 (2004)
Koushanfar, F., Qu, G., Potkonjak, M.: Intellectual Property Metering. Information Hiding, Workshop (2001)
Chakraborty, R.S., Bhunia, S.: HARPOON: an obfuscation-based soc design methodology for hardware protection. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 28(10), 1493–1502 (2009)
Intelligence Advanced Research Projects Activity. Trusted Integrated Circuits Program. https://www.fbo.gov/utils/view?id=b8be3d2c5d5babbdffc6975c370247a6
Rhrmair, U., Devadas, S., Koushanfar, F.: Security Based on Physical Unclonability and Disorder. Introduction to Hardware Security and Trust, pp. 65–102 (2012)
Holcomb, D.E., Burleson, W.P., Fu, K.: Power-up SRAM state as an identifying fingerprint and source of true random numbers. IEEE Trans. Comput. 58(9), 1198–1210 (2009)
Guajardo, Jorge, Kumar, Sandeep S., Schrijen, Geert-Jan, Tuyls, Pim: FPGA intrinsic PUFs and their use for IP protection. Cryptographic Hardware Embed. Syst. 4727, 63–80 (2007)
Tuyls, P., Schrijen, G.-J., Kori, B., van Geloven, J., Verhaegh, N., Wolters, R.: Read-proof hardware from protective coatings. Cryptographic Hardware Embed. Syst. 4249, 369–383 (2006)
Helinski, R., Acharyya, D., Plusquellic, J.: A physical unclonable function defined using power distribution system equivalent resistance variations. ACM/IEEE Design Automation Conference, pp. 676–681 (2009)
Helinski, R., Acharyya, D., Plusquellic, J.: Quality metric evaluation of a physical unclonable function derived from an IC’s power distribution system. ACM/IEEE Design Automation Conference, pp. 240–243 (2010)
Gassend, B., Clarke, D., van Dijk, M., Devadas, S.: Silicon physical random functions. ACM Conference on Computer and Communications Security, pp. 148–160 (2002)
Suh, G.E., Devadas, S.: Physical unclonable functions for device authentication and secret key generation. IEEE/ACM Design Automation Conference, pp. 9–14 (2007)
Lee, J.W., Lim, D., Gassend, B., Suh, G.E., van Dijk, M., Devadas, S.: A technique to build a secret key in integrated circuits for identification and authentication applications. IEEE Internationall Symposium on VLSI Circuits, pp. 176–179 (2004)
Majzoobi, M., Koushanfar, F., Potkonjak, M.: Lightweight secure PUFs. IEEE/ACM International Conference on Computer-Aided Design, pp. 670–673 (2008)
Pappu, R., Recht ,B., Taylor, J., Gershenfeld, N.: Physical one-way functions. Science 297(5589), 2026–2030 (2002)
Maiti, A., Gunreddy, V., Schaumont, P.: A Systematic Method to Evaluate and Compare the Performance of Physical Unclonable Functions (2011). https://eprint.iacr.org/2011/657.pdf
Devadas, S.: Non-networked RFID PUF authentication. U.S. Patent 8 683 210, U.S. Patent Appl. 12/623 045 (2008)
Suh, G.E., O’Donnell, C.W., Devadas, S.: Aegis: a single-chip secure processor. IEEE Des. Test Comput. 24(6), 570–580 (2007)
Rührmair, U., Sehnke, F., Sölter, J., Dror, G., Devadas, S., Schmidhuber, J.: Modeling attacks on physical unclonable functions. ACM Conference on Computer and Communications Security, pp. 237–249 (2010)
Schuster, D.: Side-channel analysis of physical unclonable functions (PUFs). PhD Dissertation, Technische Universität München (2010)
Wei, S., Wendt, J.B., Nahapetiany, A., Potkonjak, M.: Reverse engineering and prevention techniques for physical unclonable functions using side channels. IEEE/ACM Design Automation Conference, pp. 1–6 (2014)
Devadas, S., Yu, MDM.: Secure and robust error correction for physical unclonable functions. IEEE Des. Test 99 (2013)
Paral, Z., Devadas, S.: Reliable and efficient PUF-based key generation using pattern matching. IEEE International Symposium on Hardware-Oriented Security and Trust, pp. 128–133 (2011)
Yin, C.-E., Qu, G.: Improving PUF security with regression-based distiller. IEEE/ACM Design Automation Conference, pp. 1–6 (2013)
Nathan Beckmann and Miodrag Potkonjak. Hardware-based public-key cryptography with public physically unclonable functions. Information Hiding, pp. 206–220 (2009)
Rajendran, J., Rose, G.S., Karri, R., Potkonjak, M.: Nano-PPUF: a memristor-based security primitive. IEEE Computer Society Annual Symposium on VLSI, pp. 84–87 (2012)
Ruhrmair, U., Chen, Q., Stutzmann, M., Lugli, P., Schlichtmann, U., Csaba, G.: Towards electrical, integrated implementations of SIMPL systems. Information Security Theory and Practices. Security and Privacy of Pervasive Systems and Smart Devices, vol. 6033, pp. 277–292 (2010)
Rosenfeld, K., Gavas, E., Karri, R.: Sensor physical unclonable functions. IEEE International Symposium on Hardware-Oriented Security and Trust, pp. 112–117
Cao, Y., Zalivaka, S.S., Zhang, L., Chang, C.-H., Chen, S.: CMOS image sensor based physical unclonable function for smart phone security applications. International Symposium on Integrated Circuits, pp. 392–395 (2014)
Maes, R., Verbauwhede, I.: Physically Unclonable Functions: A Study on the State of the Art and Future Research Directions, pp. 3–37. Towards Hardware-Intrinsic, Security (2010)
Council Decision 96/644/EC of 11 November 1996 on the extension of the legal protection of topographies of semiconductor products to persons from the Isle of Man (2015). http://eur-lex.europa.eu/legal-content/EN/TXT/?uri=celex:31996D0644
Law on the Circuit Layout of a Semiconductor Integrated Circuits (Act No. 43 of May 31, 1985, as last amended by Act No. 50 of June 2, 2006) (2015)
Malbon, J., Lawson, C., Davison, M.: A Commentary. Edward Elgar Publishing, The WTO Agreement on Trade-Related Aspects of Intellectual Property Rights (2014). ISBN 9781845424435
Government Printing Office. The Copyright Law of the United States and Related Laws Contained in Title 17 of the United States Code (2012). ISBN 9780160795084
Alkabani, Y., Koushanfar, F., Potkonjak, M.: Remote activation of ICs for piracy prevention and digital right management. In: Proceedings of IEEE/ACM International Conference on Computer-Aided Design, pp. 674–677 (2007)
Alkabani, Y., Koushanfar, F.: Active Hardware Metering for Intellectual Property Protection and Security, pp. 291–306. USENIX, Security (2007)
Huang, J., Lach, J.: IC activation and user authentication for security-sensitive systems. IEEE International Workshop on Hardware-Oriented Security and Trust, pp. 76–80 (2008)
Roy, J.A., Koushanfar, F., Markov, I.L.: Protecting bus-based hardware IP by secret sharing. ACM/IEEE Design Automation Conference, pp. 846–851 (2008)
Koushanfar, F., Qu, G.: Hardware metering. IEEE/ACM Design Automation Conference, pp. 490–493 (2001)
Lofstrom, K., Daasch, W.R., Taylor, D.: IC identification circuit using device mismatch. IEEE International Solid-State Circuits Conference, pp. 372–373 (2000)
Pentium III serial numbers. http://www.pcmech.com/article/pentium-iii-serialnumbers/
Kahng, A.B., Lach, J., Mangione-Smith, W.H., Mantik, S., Markov, I.L., Potkonjak, M., Tucker, P., Wang, H., Wolfe, G.: Watermarking techniques for intellectual property protection. IEEE/ACM Design Automation Conference, pp. 776–781 (1998)
Kahng, A.B., Mantik, S., Markov, I.L., Potkonjak, M., Tucker, P., Wang, H., Wolfe, G.: Robust IP watermarking methodologies for physical design. IEEE/ACM Design Automation Conference, pp. 782–787 (1998)
Lach, J., Mangione-Smith, W.H., Potkonjak, M.: FPGA fingerprinting techniques for protecting intellectual property. IEEE Custom Integrated Circuits Conference, pp. 299–302 (1998)
Wolfe, G., Wong, J.L., Potkonjak, M.: Watermarking graph partitioning solutions. IEEE/ACM Design Automation Conference, pp. 486–489 (2001)
Alpert, C.J., Kahng, A.: Recent Directions in Netlist Partitioning. Integration, The VLSI journal (1995)
Dupuis, S., Ba, P.-S., Di Natale, G., Flottes, M.L., Rouzeyre, B.: A novel hardware logic encryption technique for thwarting illegal overproduction and hardware Trojans. IEEE International On-Line Testing Symposium, pp. 49–54 (2014)
Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: a fault analysis perspective. In: Proceedings of the IEEE/ACM Design, Automation and Test in Europe, pp. 953–958 (2012)
Rajendran, J., Zhang, H., Zhang, C., Rose, G.S., Pino, Y., Sinanoglu, O., Karri, R.: Fault analysis-based logic encryption. IEEE Trans. Comput. 64(2), 410–424 (2015)
Plaza, S.M., Markov, I.L.: Solving the third-shift problem in ic piracy with test-aware logic locking. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 34(6), 961–971 (2015)
Chakraborty, R.S., Bhunia, S.: Security against hardware Trojan through a novel application of design obfuscation. IEEE/ACM International Conference on Computer-Aided Design, pp. 113–116 (2009)
Colombier, B., Bossuet, L.: Survey of hardware protection of design data for integrated circuits and intellectual properties. IET Comput. Digital Tech. 8(6), 274–287 (2014)
Baumgarten, A., Tyagi, A., Zambreno, J.: Preventing IC piracy using reconfigurable logic barriers. IEEE Des. Test Comput. 27(1), 66–75 (2010)
Khaleghi, S., Da Zhao, K., Rao, W.: IC piracy prevention via design withholding and entanglement. Asia-Pacific Design Automation Conference, pp. 821–826 (2015)
Lee, Y.-W., Touba, N.A.: Improving logic obfuscation via logic cone analysis. IEEE Latin-American Test Symposium, pp. 1–6 (2015)
Contreras, G.K., Rahman, M.T., Tehranipoor, M.: Secure split-test for preventing ic piracy by uuntrusted foundry and assembly. IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, pp. 196–203 (2013)
Roy, J.A., Koushanfar, F., Markov, I.L.: Protecting bus-based hardware ip by secret sharing. In: Proceedings of IEEE/ACM Design Automation Conference, pp. 846–851 (2008)
Plaza, S.M., Markov, I.L.: Protecting Integrated Circuits from Piracy with Test-aware Logic Locking (2014)
Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Security analysis of logic obfuscation. IEEE/ACM Design Automation Conference, pp. 83–89 (2012)
Subramanyan, P., Ray, S., Malik, S.: Evaluating the Security of Logic Encryption Algorithms. IEEE International Symposium on Hardware Oriented Security and Trust, pp. 137–143 (2015)
Chakraborty, R.S., Bhunia, S.: Hardware protection and authentication through netlist level obfuscation. IEEE/ACM International Conference on Computer-Aided Design, pp. 674–677 (2008)
Chakraborty, R.S., Bhunia, S.: Security against hardware trojan through a novel application of design obfuscation. IEEE/ACM International Conference on Computer-Aided Design, pp. 113–116 (2009)
Chakraborty, R.S., Bhunia, S.: RTL hardware ip protection using key-based control and data flow obfuscation. IEEE International Conference on VLSI Design, pp. 405–410 (2010)
Koushanfar, Farinaz: Provably secure active IC metering techniques for piracy avoidance and digital rights management. IEEE Trans. Inf. Forensics Secur. 7(1), 51–63 (2012)
Jarvis, R.W., McIntyre, M.G.: Split manufacturing method for advanced semiconductor circuits. US Patent no. 7195931 (2004)
FreePDK45:Metal Layers. http://www.eda.ncsu.edu/wiki/FreePDK45:Metal_Layers
Jagasivamani, M., Gadfort, P., Sika, M., Bajura, M., Fritze, M.: Split fabrication obfuscation: metrics and techniques. IEEE Symposium on Hardware Oriented Security and Trust (2014)
Hill, B., Karmazin, R., Otero, C.T.O., Tse, J., Manohar, R.: A split-foundry asynchronous FPGA. IEEE Custom Integrated Circuits Conference, pp. 1–4 (2013)
Valamehr, J., Sherwood, T., Kastner, R., Marangoni-Simonsen, D., Huffmire, T., Irvine, C., Levin, T.: A 3-D split manufacturing approach to trustworthy system development. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 32(4), 611–615 (2013)
Vaidyanathan, K., Liu, R., Sumbul, E., Zhu, Q., Franchetti, F., Pileggi, L.: Efficient and secure intellectual property (IP) design for split fabrication. IEEE Symposium on Hardware Oriented Security and Trust (2014)
Naveed, A.: Sherwani. Springer Publications, Algorithms for VLSI Physical Design Automation (2002)
Rajendran, O., Sinanoglu, J., Karri, R.: Is split manufacturing secure? IEEE Design, Automation and Test in Europe Conference, pp. 1259–1264 (2013)
Vaidyanathan, K., Das, B.P., Sumbul, E., Liu, R., Pileggi, L.: Building trusted ICs using split fabrication. IEEE Symposium on Hardware Oriented Security and Trust (2014)
Imeson, F., Emtenan, A., Garg, S., Tripunitara, M.: Securing Computer Hardware Using 3D Integrated Circuit (IC) Technology and Split Manufacturing for Obfuscation. USENIX Security (2013)
Altera. Altera Reveals Stratix 10 Innovations Enabling the Industrys Fastest and Highest Capacity FPGAs and SoCs. http://newsroom.altera.com/press-releases/nr-altera-stratix10.htm
Verayo, P.: Physical unclonable function. http://www.verayo.com/tech.php
Intrinsic ID. Physical unclonable function. https://www.intrinsic-id.com/technology/physically-unclonable-functions-puf/
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2017 Springer International Publishing AG
About this chapter
Cite this chapter
Karri, R., Sinanoglu, O., Rajendran, J. (2017). Physical Unclonable Functions and Intellectual Property Protection Techniques. In: Bhunia, S., Ray, S., Sur-Kolay, S. (eds) Fundamentals of IP and SoC Security. Springer, Cham. https://doi.org/10.1007/978-3-319-50057-7_8
Download citation
DOI: https://doi.org/10.1007/978-3-319-50057-7_8
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-319-50055-3
Online ISBN: 978-3-319-50057-7
eBook Packages: EngineeringEngineering (R0)