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IP Trust: The Problem and Design/Validation-Based Solution

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Fundamentals of IP and SoC Security

Abstract

Globalization of the integrated circuit (IC) supply chain has raised security vulnerabilities at various stages of the IC design flow. Due to increasing demand for products, companies are trying to reduce the time-to-market (TTM) of ICs which, combined with the increased design complexity, boosts the intellectual property (IP) cores transaction market, and supports the growth of third-party design houses. Meanwhile, the exorbitant cost of in-house chip manufacturing and testing forces companies to outsource these services to foundries and third-party testing facilities. The use of third-party IPs and the outsourcing of fabrication and testing services have raised security concerns, thereby compelling companies to evaluate trustworthiness of their circuit designs. Many defense mechanisms have been proposed to protect IP/IC from reverse engineering, malicious tampering, piracy, counterfeiting, cloning, and overbuilding. In this chapter, we first illustrate different threats to an IP/IC as well as locations of possible adversaries in the supply chain. Subsequently, we discuss different protection methods for soft and firm IP cores. Among the two categories of protection methods, authentication, and prevention, we explain the prevention methods in greater details. We divide the prevention methods into combinational logic locking/encryption and finite state machine locking/encryption. Methods for protecting field-programmable gate array (FPGA) bitstreams are also included in the chapter. We then discuss various IP certification methods, which are used to ensure trustworthiness of IPs. Two main categories of formal methods are particularly elaborated within the scope of IP certification: theorem proving and equivalence checking.

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Acknowledgements

This work was supported in part by the National Science Foundation (CNS-1319105).

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Authors and Affiliations

  1. University of Central Florida, Orlando, FL, USA

    Raj Gautam Dutta, Xiaolong Guo & Yier Jin

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  1. Raj Gautam Dutta
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  2. Xiaolong Guo
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  3. Yier Jin
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Correspondence to Raj Gautam Dutta .

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Editors and Affiliations

  1. University of Florida , Gainesville, Florida, USA

    Swarup Bhunia

  2. NXP Semiconductors (United States) , Austin, Texas, USA

    Sandip Ray

  3. Advanced Computing and Microelectronics, Indian Statistical Institute, Kolkata, India

    Susmita Sur-Kolay

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Dutta, R.G., Guo, X., Jin, Y. (2017). IP Trust: The Problem and Design/Validation-Based Solution. In: Bhunia, S., Ray, S., Sur-Kolay, S. (eds) Fundamentals of IP and SoC Security. Springer, Cham. https://doi.org/10.1007/978-3-319-50057-7_4

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  • DOI: https://doi.org/10.1007/978-3-319-50057-7_4

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  • Online ISBN: 978-3-319-50057-7

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