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SAT-Based Combinational and Sequential Dependency Computation

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Hardware and Software: Verification and Testing (HVC 2016)

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Abstract

We present an algorithm for computing both functional dependency and unateness of combinational and sequential Boolean functions represented as logic networks. The algorithm uses SAT-based techniques from Combinational Equivalence Checking (CEC) and Automatic Test Pattern Generation (ATPG) to compute the dependency matrix of multi-output Boolean functions. Additionally, the classical dependency definitions are extended to sequential functions and a fast approximation is presented to efficiently yield a sequential dependency matrix. Extensive experiments show the applicability of the methods and the improved robustness compared to existing approaches.

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Notes

  1. 1.

    We also performed a structural check for each input-output pair if there potentially exists an inverting path between them. If this is not the case, the additionally SAT-call to check for unateness may be skipped. However, the performance impact was insignificant and hence we did not employ this optimization.

  2. 2.

    lsi.epfl.ch/benchmarks.

  3. 3.

    In [29] shift-left and shift-right are considered separately. Since these operations are equivalent under permutation, the measured numbers in the experiment also do not differ.

References

  1. Biere, A., Cimatti, A., Clarke, E.M., Fujita, M., Zhu, Y.: Symbolic model checking using SAT procedures instead of BDDs. In: Design Automation Conference, pp. 317–320 (1999)

    Google Scholar 

  2. Albrecht, C.: IWLS 2005 benchmarks. In: International Workshop for Logic Synthesis (IWLS) (2005). http://www.iwls.org

  3. Biere, A., Heule, M.J.H., van Maaren, H., Walsh, T. (eds.): Handbook of Satisfiability, Frontiers in Artificial Intelligence and Applications, vol. 185. IOS Press, Amsterdam (2009)

    Google Scholar 

  4. Brayton, R., Mishchenko, A.: ABC: an academic industrial-strength verification tool. In: Touili, T., Cook, B., Jackson, P. (eds.) CAV 2010. LNCS, vol. 6174, pp. 24–40. Springer, Heidelberg (2010). doi:10.1007/978-3-642-14295-6_5

    Chapter  Google Scholar 

  5. Bryant, R.E.: Graph-based algorithms for Boolean function manipulation. IEEE Trans. Comput. 35(8), 677–691 (1986)

    Article  MATH  Google Scholar 

  6. Cook, S.A.: The complexity of theorem-proving procedures. In: Symposium on Theory of Computing, pp. 151–158 (1971)

    Google Scholar 

  7. Corno, F., Reorda, M., Squillero, G.: RT-level ITC’99 benchmarks and first ATPG results. IEEE Des. Test Comput. 17(3), 44–53 (2000)

    Article  Google Scholar 

  8. Saab, D.G., Abraham, J.A., Vedula, V.M.: Formal verification using bounded model checking: SAT versus sequential ATPG engines. In: VLSI Design, pp. 243–248 (2003)

    Google Scholar 

  9. Een, N., Mishchenko, A., Sörensson, N.: Applying logic synthesis for speeding up SAT. In: Marques-Silva, J., Sakallah, K.A. (eds.) SAT 2007. LNCS, vol. 4501, pp. 272–286. Springer, Heidelberg (2007). doi:10.1007/978-3-540-72788-0_26

    Chapter  Google Scholar 

  10. Eén, N., Sörensson, N.: An extensible SAT-solver. In: Giunchiglia, E., Tacchella, A. (eds.) SAT 2003. LNCS, vol. 2919, pp. 502–518. Springer, Heidelberg (2004). doi:10.1007/978-3-540-24605-3_37

    Chapter  Google Scholar 

  11. van Eijk, C.A.J., Jess, J.A.G.: Exploiting functional dependencies in finite state machine verification. In: European Design and Test Conference, pp. 9–14 (1996)

    Google Scholar 

  12. Jiang, J.-H.R., Brayton, R.K.: Functional dependency for verification reduction. In: Alur, R., Peled, D.A. (eds.) CAV 2004. LNCS, vol. 3114, pp. 268–280. Springer, Heidelberg (2004). doi:10.1007/978-3-540-27813-9_21

    Chapter  Google Scholar 

  13. Jiang, J.R., Lee, C., Mishchenko, A., Huang, C.: To SAT or not to SAT: scalable exploration of functional dependency. IEEE Trans. Comput. 59(4), 457–467 (2010)

    Article  MathSciNet  Google Scholar 

  14. Katebi, H., Markov, I.L.: Large-scale Boolean matching. In: Design, Automation and Test in Europe, pp. 771–776 (2010)

    Google Scholar 

  15. Larrabee, T.: Test pattern generation using Boolean satisfiability. IEEE Trans. CAD Integr. Circuits Syst. 11(1), 4–15 (1992)

    Article  Google Scholar 

  16. Lee, C., Jiang, J.R., Huang, C., Mishchenko, A.: Scalable exploration of functional dependency by interpolation and incremental SAT solving. In: International Conference on Computer-Aided Design, pp. 227–233 (2007)

    Google Scholar 

  17. Levin, L.A.: Universal sequential search problems. Probl. Inf. Transm. 9(3), 115–116 (1973)

    MATH  Google Scholar 

  18. Sheeran, M., Singh, S., Stålmarck, G.: Checking safety properties using induction and a SAT-solver. In: Hunt, W.A., Johnson, S.D. (eds.) FMCAD 2000. LNCS, vol. 1954, pp. 127–144. Springer, Heidelberg (2000). doi:10.1007/3-540-40922-X_8

    Chapter  Google Scholar 

  19. Marhöfer, M.: An approach to modular test generation based on the transparency of modules. In: IEEE CompEuro 1987, pp. 403–406 (1987)

    Google Scholar 

  20. McMillan, K.L.: Interpolation and SAT-based model checking. In: Hunt, W.A., Somenzi, F. (eds.) CAV 2003. LNCS, vol. 2725, pp. 1–13. Springer, Heidelberg (2003). doi:10.1007/978-3-540-45069-6_1

    Chapter  Google Scholar 

  21. McNaughton, R.: Unate truth functions. IRE Trans. Electron. Comput. 10(1), 1–6 (1961)

    Article  MathSciNet  Google Scholar 

  22. Mishchenko, A., Chatterjee, S., Brayton, R.K., Eén, N.: Improvements to combinational equivalence checking. In: International Conference on Computer-Aided Design, pp. 836–843 (2006)

    Google Scholar 

  23. Mohnke, J., Molitor, P., Malik, S.: Limits of using signatures for permutation independent Boolean comparison. Form. Methods Syst. Des. 21(2), 167–191 (2002)

    Article  MATH  Google Scholar 

  24. Murray, B.T., Hayes, J.P.: Test propagation through modules and circuits. In: International Test Conference, pp. 748–757 (1991)

    Google Scholar 

  25. Reimer, S., Sauer, M., Schubert, T., Becker, B.: Using MaxBMC for pareto-optimal circuit initialization. In: Conference on Design, Automation and Test in Europe, pp. 1–6, March 2014

    Google Scholar 

  26. Sauer, M., Becker, B., Polian, I.: PHAETON: a SAT-based framework for timing-aware path sensitization. IEEE Trans. Comput. PP(99), 1 (2015)

    MathSciNet  Google Scholar 

  27. Sauer, M., Reimer, S., Polian, I., Schubert, T., Becker, B.: Provably optimal test cube generation using quantified Boolean formula solving. In: ASP Design Automation Conference, pp. 533–539 (2013)

    Google Scholar 

  28. Schubert, T., Reimer, S.: antom (2013). https://projects.informatik.uni-freiburg.de/projects/antom

  29. Soeken, M., Sterin, B., Drechsler, R., Brayton, R.K.: Reverse engineering with simulation graphs. In: Formal Methods in Computer-Aided Design, pp. 152–159 (2015)

    Google Scholar 

  30. Solnon, C.: AllDifferent-based filtering for subgraph isomorphism. Artif. Intell. 174(12–13), 850–864 (2010)

    Article  MathSciNet  MATH  Google Scholar 

  31. Stephan, P., Brayton, R.K., Sangiovanni-Vincentelli, A.L.: Combinational test generation using satisfiability. IEEE Trans. CAD Integr. Circuits Syst. 15(9), 1167–1176 (1996)

    Article  Google Scholar 

  32. Tseytin, G.: On the complexity of derivation in propositional calculus. In: Studies in Constructive Mathematics and Mathematical Logic (1968)

    Google Scholar 

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Acknowledgments

The authors wish to thank Robert Brayton and Alan Mishchenko for many helpful discussions. This research was partially financed by H2020-ERC-2014-ADG 669354 CyberCare and the Baden-Württemberg Stiftung gGmbH Stuttgart within the scope of its IT security research programme.

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Soeken, M., Raiola, P., Sterin, B., Becker, B., De Micheli, G., Sauer, M. (2016). SAT-Based Combinational and Sequential Dependency Computation. In: Bloem, R., Arbel, E. (eds) Hardware and Software: Verification and Testing. HVC 2016. Lecture Notes in Computer Science(), vol 10028. Springer, Cham. https://doi.org/10.1007/978-3-319-49052-6_1

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  • DOI: https://doi.org/10.1007/978-3-319-49052-6_1

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