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Hardware Hardening Approaches Using Camouflaging, Encryption, and Obfuscation

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Hardware IP Security and Trust

Abstract

Due to the trend of globalized semiconductor supply chain, integrated circuits (IC) and hardware intellectual property (IP) are prone to serious security threats such as reverse engineering and IP piracy. In addition to the post-fabrication authentication techniques (e.g., IP metering), various hardware hardening approaches have emerged to resist reverse engineering and IP piracy. This chapter reviews three representable security hardening approaches—camouflaging, logic encryption/locking, and design obfuscation—that are applied to ICs at layout, gate, and register transfer levels. Particularly, this chapter presents a dynamic state-deflection-based obfuscation method, which deflects the state transition from the original transition path to a black hole cluster if an invalid key is applied to the hardware IP. This obfuscation method can successfully thwart the reverse engineering attack that exploits the code analysis support from electronic design automation (EDA) tools. Furthermore, this chapter extends the idea of design obfuscation for two-dimensional IC to emerging three-dimensional (3D) IC design technology. The proposed method is based on the insertion of a Network-on-Chip (NoC)-based shielding plane between two commercial dies to build the secure 3D ICs without involvement of trustworthy foundries.

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Author information

Authors and Affiliations

  1. University of New Hampshire, Durham, NH, 03824, USA

    Qiaoyan Yu & Jaya Dofe

  2. Ningbo University, Ningbo, Zhejiang, China

    Yuejun Zhang

  3. Charles Stark Draper Laboratory, Inc., Cambridge, MA, 02139, USA

    Jonathan Frey

Authors
  1. Qiaoyan Yu
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  2. Jaya Dofe
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  3. Yuejun Zhang
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  4. Jonathan Frey
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Correspondence to Qiaoyan Yu .

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Editors and Affiliations

  1. Department of Computer and Information Science and Engineering, University of Florida , Gainesville, Florida, USA

    Prabhat Mishra

  2. Department of Electrical and Computer Engineering, University of Florida , Gainesville, Florida, USA

    Swarup Bhunia

  3. Department of Electrical and Computer Engineering, University of Florida , Gainesville, Florida, USA

    Mark Tehranipoor

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Yu, Q., Dofe, J., Zhang, Y., Frey, J. (2017). Hardware Hardening Approaches Using Camouflaging, Encryption, and Obfuscation. In: Mishra, P., Bhunia, S., Tehranipoor, M. (eds) Hardware IP Security and Trust. Springer, Cham. https://doi.org/10.1007/978-3-319-49025-0_7

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  • DOI: https://doi.org/10.1007/978-3-319-49025-0_7

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