Electrical Characterization of Semiconductor Materials and Devices

Part of the Springer Handbooks book series (SPRINGERHAND)


Semiconductor materials and devices continue to occupy a preeminent technological position due to their importance when building integrated electronic systems used in a wide range of applications from computers, cell-phones, personal digital assistants, digital cameras and electronic entertainment systems, to electronic instrumentation for medical diagnositics and environmental monitoring. Key ingredients of this technological dominance have been the rapid advances made in the quality and processing of materials – semiconductors, conductors and dielectrics – which have given metal oxide semiconductor device technology its important characteristics of negligible standby power dissipation, good input–output isolation, surface potential control and reliable operation. However, when assessing material quality and device reliability, it is important to have fast, nondestructive, accurate and easy-to-use electrical characterization techniques available, so that important parameters such as carrier doping density, type and mobility of carriers, interface quality, oxide trap density, semiconductor bulk defect density, contact and other parasitic resistances and oxide electrical integrity can be determined. This chapter describes some of the more widely employed and popular techniques that are used to determine these important parameters. The techniques presented in this chapter range in both complexity and test structure requirements from simple current–voltage measurements to more sophisticated low-frequency noise, charge pumping and deep-level transient spectroscopy techniques.

The continued evolution of semiconductor devices to smaller dimensions in order to improve performance – speed, functionality, integration density and reduced cost – requires layers or films of semiconductors, insulators and metals with increasingly high quality that are well-characterized and that can be deposited and patterned to very high precision. However, it is not always the case that improvements in the quality of materials have kept pace with the evolution of integrated circuit down-scaling. An important aspect of assessing the material quality and device reliability is the development and use of fast, nondestructive and accurate electrical characterization techniques to determine important parameters such as carrier doping density, type and mobility of carriers, interface quality, oxide trap density, semiconductor bulk defect density, contact and other parasitic resistances and oxide electrical integrity. This chapter will discuss several techniques that are used to determine these important parameters. However, it is not an extensive compilation of the electrical techniques currently used by the research and development community; rather, it presents a discussion of some of the more widely used and popular ones [20.1, 20.2, 20.3, 20.4].

An important aspect of electrical characterization is the availability of appropriate test components [20.1, 20.2, 20.3, 20.4]. In this chapter, we concentrate on discussing techniques that use standard test devices and structures. In addition, we will use the metal–oxide–semiconductor field-effect transistor (MOSFET ) whenever possible because they are widely available on test chips. This is also motivated by the fact that MOSFETs continue to dominate the semiconductor industry for a wide range of applications from memories and microprocessors to signal and imaging processing systems [20.5]. A key reason for this dominance is the excellent quality of the silicon wafers and the silicon–silicon dioxide interface, both of which play critical roles in the performance and reliability of the device. For example, if the interface has many defects or interface states, or it is rough, then the device’s carrier mobility decreases, low-frequency noise increases and its performance and reliability degrades. In particular, it is not only the interface that is important, but also the quality of the oxide; good-quality oxide prevents currents from flowing between the gate and substrate electrodes through the gate oxide. Both interface and oxide quality allows for excellent isolation between the input and output terminals of the MOSFETs, causing it to behave as an almost ideal switch. Therefore, it is important to have good experimental tools to study the interface properties and the quality of the gate dielectric.

Electrical characterization of semiconductors and the semiconductor–dielectric interface is important for a variety of reasons. For example, the defects at and in the interfacial oxide layer in silicon–silicon dioxide (Si–SiO2) systems and in the bulk semiconductor play critical roles in their low-frequency noise, independent of whether the device is surface-controlled such as a MOSFET, or a bulk transport device such as a polysilicon emitter bipolar junction transistor (PE BJT ). These defects can affect the charge transfer efficiency in charge coupled devices (CCD s), p–n photodiodes or complementary metal-oxide-semiconductor (CMOS ) imagers, and can be the initiation point of catastrophic failure of oxides. Interface and bulk states can act as scattering centers to reduce the mobility in MOSFETs, thus affecting their performance parameters such as switching speed, transconductance and noise. This chapter is devoted to the electrical characterization of semiconductors, insulators and interfaces. In the first part (Sects. 20.1 and 20.2 ), the basic electrical properties of materials (such as resistivity, concentration and mobility of carriers) are studied. The main measurement techniques used to determine these electrical parameters are presented. Due to its increasing importance in modern ultrasmall geometry devices, electrical contacts are also studied. All of the characterization techniques presented in this first part are associated with specially designed test structures. In the second part (Sects. 20.420.7 ), we use active components such as capacitors, diodes and transistors (mainly MOSFETs) in order to determine more specific electrical parameters such as traps, oxide quality and noise level that are associated with material or devices. Of course this involves specific measurement techniques that are often more sophisticated than those discussed in the previous two sections.

20.1 Resistivity

Resistivity is one of the most important electrical parameters of semiconductors [20.1, 20.2, 20.3, 20.4]. First, we present the basic physical relations concerning the bulk resistivity. The main electrical measurement techniques are then described: the two oldest ones that are still relevant today – the four-point-probe technique and the van der Pauw technique – and then the spreading resistance technique. Second, because it is closely linked with bulk resistivity measurement techniques and it is increasingly important in modern ultrasmall geometry devices, contact resistivity will be presented. Special attention will be given to Kelvin contact resistance (KCR ) measurement and the transmission line measurement (TLM ) techniques.

20.1.1 Bulk Resistivity

Physical Approach, Background and Basics

The bulk resistivity ρ is an intrinsic electrical property related to carrier drift in materials such as metals and semiconductors [20.6]. From a macroscopic point of view, the resistivity ρ can be viewed as the normalization of the bulk resistance ( R )  by its geometrical dimensions – the cross-sectional area ( A = Wt )  through which the current flows, and the distance between the two ideal contacts L, as shown in Fig. 20.1 . The resistivity is given by
$$\rho=\frac{RA}{L}\quad\text{in }{\mathrm{\Upomega{\,}m}}\text{ or commonly }{\mathrm{\Upomega{\,}cm}}.$$
For thin semiconductor layers, the sheet resistivity ρs is often used instead of the bulk resistivity ρ. The sheet resistivity ρs is the bulk resistivity divided by the sample’s thickness t. This normalized parameter is related to the resistance of a square of side L. For this particular geometry in Fig. 20.1 , since A = Wt, then ρs = R, the sheet resistance. The unit of sheet resistance is Ω/square or Ω∕ □. The parameter R is convenient for integrated circuit designers because it allows them to quickly design the geometry for a specific value of resistance using very thin implanted or diffused semiconductor regions or polycrystalline layers. Resistivity (or its inverse, the conductivity σ in \(\mathrm{\Upomega{}^{-1}{\,}cm^{-1}}\) or S ∕ cm) and its variation with temperature is often used to classify material into metals, semiconductors and insulators.
Fig. 20.1

Bulk resistance and its geometrical dimensions

Since different semiconductors can have the same resistivity, and also different values of resistivity can be found for a given semiconductor, depending on how it is processed for example, then resistivity is not a fundamental material parameter. From solid state theory, in the case of homogeneous semiconductor materials, the resistivity expresses the proportionality between the applied electric field E and the drift current density J; that is, \(J=\left(1/\rho\right)E\). It can be defined by the microscopic relation
where q is the electronic charge, n and p are the free electron and hole concentrations, and μ n and μ p are the electron and hole drift mobilities, respectively. In this way, the resistivity is related to fundamental semiconductor parameters: the number of free carriers, and their ability to move in the lattice when an electric field is applied.
In n-type or donor ( ND ) -doped, or p-type or acceptor ( NA ) -doped semiconductors, the free carrier densities are determined by the ionized impurities (ND or NA ≫  the intrinsic carrier concentration ni), then (20.2 ) can be simplified to
$$\rho \approx\frac{1}{qn\mu_{n}}\;,\;\text{for an n-type semiconductor}\;,$$
$$\text{and}\;\rho \approx\frac{1}{qp\mu_{p}}\;,\;\text{for a p-type semiconductor}\;.$$
In the following sections, only single-type semiconductors will be studied. This corresponds to most semiconductor materials used in electronic and optoelectronic devices because either ND ≫ NA or NA ≫ ND in a typical semiconductor layer.

Measurement Techniques

The simplest way to determine bulk resistivity is to measure the voltage drop along a uniform semiconductor bar through which a direct current (DC ) I flows, as shown in Fig. 20.1. Thus, the measured resistance and knowledge of the geometrical dimensions can lead to an estimate for the bulk resistivity according to (20.1). Unfortunately the measured resistance ( Rmea )  includes the unexpected contact resistance ( 2Rc ) , which can be significant for small-geometry samples because Rc is strongly dependent on the metal-semiconductor structure. Therefore, special processing technologies are used to minimize the influence of Rc (Sect. 20.1.2). Now, the measured resistance is expressed as
If probes are used instead of large metal-semiconductor contacts, then the spreading resistance ( Rsp )  under the two probes must also be added, as shown in Fig. 20.2. In this case, (20.5) becomes
where Rsp for a cylindrical contact of radius r, and for a semi-infinite sample, it can be expressed by
For a hemispherical contact of radius r, Rsp is given by
$$R_{\mathrm{sp}}=\frac{\rho}{2\uppi r}\;.$$
In both cases, it is very difficult to provide a direct measurement or an accurate model of the contact resistance. So determining the bulk resistivity by this approach is not recommended, except when the spreading resistance is the dominant term in (20.6) and when (20.7) or (20.8 ) can be applied. In this case, the resistivity is determined by the spreading resistance technique measurement. Nevertheless, despite the lack of accuracy of the two contact techniques, it can be sufficient for monitoring some process steps and it is often used in the semiconductor industry as a process monitor.
Fig. 20.2

Spreading resistance associated with a probe contact

Four-Point Probe Technique
In order to eliminate or at least minimize the contact contribution to the measured resistance value, techniques based on separate current injection and voltage drop measurements have been developed. First, the two-probe technique can be used, as reported in Fig. 20.1. This measurement is very simple, but it is affected by several parameters: lateral contact geometry, probe spacing, and minority carrier injection near the lateral contacts. The main disadvantage of this technique is the need for lateral contacts. This requirement is overcome with the four-point probe technique, where two probes are used for current injection and the other two probes are used to measure the voltage drop. The more usual probe geometry configuration is when the four probes are placed in a line, as shown in Fig. 20.3.
Fig. 20.3

Linear four-point probe configuration. The sample thickness is t and a is the distance from the edge or boundary of the sample

The voltage at probe 2, V2, induced by the current flowing from probe 1 to probe 4 is given by:
$$V_{2}=\frac{\rho I}{2\uppi}\left({\frac{1}{s_{1}}-\frac{1}{s_{2}+s_{3}}}\right).$$
The voltage at probe 3 is
$$V_{3}=\frac{\rho I}{2\uppi}\left({\frac{1}{s_{1}+s_{2}}-\frac{1}{s_{3}}}\right).$$
Then, by measuring\(V=V_{2}-V_{3}\), the voltage drop between probes 2 and 3, and the current I through probes 1 and 4, the resistivity can be determined using (20.9a) and (20.9b) as
$$\rho=\frac{2\uppi V/I}{\left(\frac{1}{s_{1}}+\frac{1}{s_{2}}-\frac{1}{s_{2}+s_{3}}-\frac{1}{s_{1}+s_{2}}\right)}$$
Thus, a direct measurement of the resistivity can be made using a high-impedance voltmeter and a current source. When the probe spacings are equal (\(s_{1}=s_{2}=s_{3}=s\)), which is the most practical case, then (20.10) becomes
$$\rho=2\uppi s\frac{V}{I}\;.$$
Equations (20.10) and (20.11 ) are valid only for semi-infinite samples; that is, when both t and the sample surface are very large (→ ∞ ) , and the probes’ locations must be far from any boundary. Because these relations can be applied only to large ingots, then in many cases a correction factor f must be introduced in order to take into account the finite thickness and surface of the sample and its boundary effects. Further, for epitaxial layers, f must also consider the nature of the substrate – whether it is a conductor or an insulator. Thus, (20.11 ) becomes
$$\rho=2\uppi s\frac{V}{I}f\;.$$
For a thin semiconductor wafer or thin semiconducting layer deposited on an insulating substrate, and for the condition \(t<s/2\), which represents most practical cases because the probe spacing s is usually on the order of a millimeter, then the correction factor due to the thickness is
$$f=\frac{\left(t/s\right)}{2\ln 2}\;\;\text{so that}\;\;\rho=4.532t\frac{V}{I}\;.$$
The noninfinite sample surface must be corrected if the ratio of the wafer diameter to the probe spacing is not greater than 40, otherwise a correction factor of less than unity has to be introduced [20.3].

If the probe header is too close to any boundary, then (20.13) is no longer valid and another correction factor must be introduced. This correction factor is close to 1 until the ratio a ∕ s is greater than 2, where a is the distance from the edge of the sample that is shown in Fig. 20.3. A study of various 8 inch n- and p-type silicon wafers have demonstrated that the edge exclusion limit is 5 mm [20.7].

In the case of a different arrangement of probes, for instance a square array or when a different measurement configuration of the four-point collinear probes is used, such as current injection between probes 1 and 3, other specific correction factors are required. Here, rather than detail all the different correction factors, complementary information can be found in [20.4, Chap. 4] and [20.3, Chap. 1].

Taking into account the appropriate correction factors as well as some specific material parameters such as hardness or surface oxidation, it is possible to map the resistivities of different types of semiconductor wafers or deposited semiconductor layers with an accuracy better than 1% over a large range of resistivity values using commercial equipment and appropriate computational techniques.

Van der Pauw Technique
Based on the same basic principle of separating the current injection and voltage measurement, the van der Pauw [20.8] measurement technique allows for the determination of resistivity on a sample of arbitrary shape using four small contacts placed on the periphery, as shown in Fig. 20.4. Then, the resistivity of a uniform sample of thickness t is given by
$$\rho=\frac{\uppi t}{\ln 2}\frac{(R_{\mathrm{A}}+R_{\mathrm{B}})}{2}f\;.$$
Here, RA and RB are resistances measured by injecting current on two adjacent contacts and by measuring the voltage drop on the two remaining ones. With the notation in Fig. 20.4, one can define
$$\begin{aligned}\displaystyle&\displaystyle R_{\mathrm{A}}=\frac{V_{3}-V_{4}}{I_{1,2}}\;,\quad R_{\mathrm{B}}=\frac{V_{4}-V_{1}}{I_{2,3}}\;,\\ \displaystyle&\displaystyle f\text{ is a correction factor that is}\\ \displaystyle&\displaystyle\text{a function of the ratio}\quad R_{f}=\frac{R_{\mathrm{A}}}{R_{\mathrm{B}}}\;.\end{aligned}$$
with R f obtained from
$$\frac{(R_{f}-1)}{(R_{f}+1)}=\frac{f}{\ln 2}{\text{arccosh}}\left({\frac{\exp\left(\ln 2/f\right)}{2}}\right).$$
In the case of samples with symmetrical geometries, and when the contacts are also symmetrical, as shown in Fig. 20.5, then RA = RB, R f  = 1 and f = 1, and (20.14) becomes
$$\rho=\frac{\uppi t}{\ln 2}R_{\mathrm{A}}=4.532tR_{\mathrm{A}}\;.$$
In order to minimize errors caused by the finite dimensions of the contacts (since ideally the contact area should be zero) and the finite thickness of the sample, then the distance between the contacts must be larger than both the diameter and the thickness of the contact. Also, the cloverleaf configuration in Fig. 20.5d is recommended to prevent contact misalignment, but this configuration requires a more complicated patterning technology.
Fig. 20.4

van der Pauw method for an arbitrarily shaped sample

Fig. 20.5a–d

Symmetrical van der Pauw structures: (a) square, (b) Greek cross, (c) circle and (d) cloverleaf

The main advantage of the van der Pauw technique compared to the four-point probe technique is its use of a smaller area for the test structure. Therefore, this measurement technique is often used in integrated circuit technology. Also, because of its simple structure, the Greek cross configuration in Fig. 20.5b is widely used (experimental results obtained on SiGeC epitaxial layers are reported in Fig. 20.6 as an example). However, when narrows arms are used, current crowding at the corners may have a significant influence, and in this case a different Greek cross layout can be considered to reduce this current crowding effect [20.9].
Fig. 20.6

Resistivity versus carrier concentration in Si\({}_{1-x-y}\)Ge x C y films obtained using a cloverleaf van der Pauw structure. (After [20.10])

Spreading Resistance Technique

The spreading resistance technique is based on the modeling of current spreading from a probe tip or a small metallic contact and flowing into a bulk semiconductor, as shown previously in Fig. 20.2. Equations (20.7) and (20.8) presented above are for cylindrical probes and hemispherical probes, respectively. Basically, the principle of this method is opposite to the previous four-contact techniques where the separation of the current injection from the measured voltage drop was used to avoid the spreading resistance. Here, the spreading resistance is expected to be the dominant term in (20.6). Only two contacts are needed: two closely aligned probes, a small top contact probe or a metallic contact and a large bottom contact. In the first case, surface mapping can be performed, but the main use of this compact probe configuration is for resistivity profiling using a bevelled sample [20.3]. The second configuration has been used to measure the substrate resistivity of silicon integrated circuits where simple test structures – for example the square top contact of 25 μm × 25 μm and 50 μm × 50 μm shown in [20.12] – have been included on a test chip.

More recently, semiconductor resistivity has been nanocharacterized using scanning spreading resistance microscopy (SSRM ) with a standard atomic force microscope (AFM ) of lateral resolution of 10 to 20 nm. A SSRM image of a 0.5 μm nMOSFET is given in Fig. 20.7a [20.11]. The resistance is low in the highly doped regions (dark) and high in the lower doped regions (bright): source, drain, gate and well regions are clearly observed in Fig. 20.7a or the resistance profile in Fig. 20.7b. With such a high resolution, scanning the lateral and vertical diffusion of dopants in active regions of submicron transistors is possible. An example is shown in Fig. 20.7c where the extra implantations (halo and lightly doped drain (LDD )) in a 0.35 μm nMOSFET process are clearly visible and result in a change of Leff from 295 nm without extra implantations to 229 nm with the extra implantations.
Fig. 20.7

(a) SSRM resistance image (scan size: 1.5 μm × 1.5 μm) of a 0.5 μm nMOSFET; (b) lateral section taken 10 nm under the gate oxide of the same transistor; (c) lateral carrier concentration profiles measured with SSRM 10 nm under the gate oxide for two 0.35 μm nMOSFETs (with and without halo and LDD process). (After [20.11])

20.1.2 Contact Resistivity

The contact resistance of an active device and interconnection becomes larger as the dimensions are scaled down. As a consequence, the performance of single transistors as well as integrated circuits can be seriously limited by increasing RC time constants and power consumption. This is of major interest for the semiconductor industry, as reported by the International Technology Roadmap for Semiconductors, ITRS 2001 [20.5], and in [20.13].

Contact Resistance Elements

Basically, the contact resistance Rc is the resistance localized from a contact pad, a probe or from the metallization process to an active region. However, it does not include all of the access resistances between these two regions, as shown in Fig. 20.8a for a horizontal contact and Fig. 20.8b for a vertical contact.
Fig. 20.8

(a) Horizontal contact and (b) vertical contact. Black indicates the metallic conductor, white the semiconductor material or an insulator

Starting from the contact pad (Figs. 20.8a and 20.9 ), the contact resistance includes the resistance of the metal Rm, the interfacial metal-semiconductor resistance Ri, and the resistance associated with the semiconductor just below the contact in the contact region Rsc. Thus, the contact resistance can be expressed as
The last component Rsc cannot be accurately defined because the boundary between the contact and access regions is very difficult to determine due to (for example) interdiffusion of metal and semiconductor atoms, and because the current flow into this region is not homogeneous due to current spreading and lateral or vertical current crowding at the periphery of the contact. The relative importance of each component of Rc is strongly dependent on different parameters of the process itself – annealing temperature, doping density and the geometry used (lateral or vertical).
Fig. 20.9

Different components of the contact resistance

When comparing different contact technologies and different contact areas, the most convenient parameter to use is the contact resistivity ρc, which is referred to as the specific contact resistance in Ω cm2, and ρc is given by
where Aceff is the effective contact area; that is, the current injection area. The concept of an effective contact area can be approximated by the contact geometry in the case of a vertical contact in Fig. 20.8b. However, Aceff is more difficult to specify for a lateral contact, where a transfer length LT, representing the length where the current flow transfers from the contact into the semiconductor just underneath, must be introduced, as shown in Fig. 20.8a. LT is defined as the length over which the voltage drops to e−1 of its value at the beginning of the contact [20.3], and is given by
where ρsc is the sheet resistivity of the semiconductor below the contact.
Because of its various components, it is difficult to accurately model the contact resistivity. Nevertheless, a theoretical approach to the interfacial resistivity (see Ri in (20.18 )), ρi, can be determined from the well-known Schottky theory of metal–semiconductor contacts. The interfacial resistivity ρi is defined by
$$\rho_{\mathrm{i}}=\left.{\frac{\partial V}{\partial J}}\right|_{V=0}\;.$$
This metal–semiconductor structure is equivalent to an abrupt p-n junction. According to the Schottky theory (for more details see [20.14, Chap. 5]), the JV characteristic of a metal–semiconductor contact in the case of a low-doped semiconductor is given by
where A is Richardson’s constant, and T the absolute temperature. φB is the barrier height formed at the metal–semiconductor interface – the difference between the vacuum level and the Fermi level of the metal and of the semiconductor materials respectively, and φB is given by
where φM is the metal work function and χ the semiconductor electron affinity.
The energy band diagram for a low-doped n-type semiconductor–metal contact is shown in Fig. 20.10 . In this case, the current transport is dominated by the thermionic emission current, resulting in a rectifying contact.
Fig. 20.10

Energy-band diagram of an n-type semiconductor–metal contact and related rectifying contact. W is the width of the depletion layer

Thus, when the conduction mechanism is controlled by the thermionic emission (TE), the interfacial resistivity in (20.21) is simply obtained from the derivative of (20.22), and ρi,TE is
Due to the presence of surface states, the barrier height φB is positive and weakly dependent on the metal–semiconductor material. φB is \(\approx 2E_{\mathrm{g}}/3\) for an n-type semiconductor and \(\approx E_{\mathrm{g}}/3\) for a p-type semiconductor. Therefore, high values of interfacial resistivity ρi,TE are usually obtained except when narrow bandgap semiconductors are used.
The way to fabricate ohmic contacts with low contact resistivity values is to process the metal on a heavily doped semiconductor layer. In this case, the depletion width decreases (\(W\approx N_{\mathrm{D}}^{-1/2}\)) and the probability of carrier tunneling through the barrier increases. Thus, the conduction mechanism is dominated by tunneling, as shown in Fig. 20.11.
Fig. 20.11

Energy-band diagram of an n+-n semiconductor–metal structure and related ohmic contact

The electron tunneling current is expressed as
εs is the permittivity of the semiconductor and m n is the effective mass of the electron.
From (20.21), (20.25) and (20.26), the interfacial resistivity ρi,T is found to be
Comparing ρi,TE from (20.24) to ρi,T from (20.27), we see that a highly doped layer can significantly reduce the interfacial resistivity. For \(N_{\mathrm{D}}\geq{\mathrm{10^{19}}}\,{\mathrm{cm^{-3}}}\), the tunneling process dominates the interfacial resistivity, while for \(N_{\mathrm{D}}\leq{\mathrm{10^{17}}}\,{\mathrm{cm^{-3}}}\), the thermionic emission current is dominant.

As most semiconductors such as Si, SiGe, GaAs, InP are of relatively wide bandgap, the deposition of a heavily doped layer before the metallization is commonly used in order to form a tunneling contact. For compound semiconductor manufacturing processes, the contact layer is generally formed from the same semiconductor material, or at least from the same material as the substrate. For silicon and related materials such as SiGe alloys or polysilicon, silicidation techniques are commonly used to make the contact layer with very thin silicide layers such as CoSi2 or TiSi2 layers.

Measurement Techniques

As mentioned above, it is difficult to accurately model the contact resistance, so direct measurements of the contact resistance or of the contact resistivity are of great importance. The two main test structures used to determine contact characteristics will now be discussed: the cross Kelvin resistor (CKR ) test structure and the transmission line model (TLM) structure.

Kelvin Test Structure
The Kelvin test structure, also referred to as the cross Kelvin resistor (CKR) test structure, is shown in Fig. 20.12. The contact resistance Rc is determined from the potential drop in the contact window (V34) when a current I is forced through the contact window from contact pad 1 to pad 2, and Rc is
Therefore, a measure of Rc and knowledge of the contact area A allows for direct extraction of the contact resistivity ρc, given by
This basic approach is not valid when parasitic effects are present. One of the main problems is current crowding around the contact. In order to extract accurate values for the contact resistivity using Kelvin test structures, it is necessary to take into account the two-dimensional current-crowding effect. This is achieved using the results from numerical simulations [20.15]. Nevertheless, the development of ohmic contacts with very low values of contact resistivities require complex technology with different materials and usually with several interfaces. In this case, a large discrepancy between the extracted and the measured contact parameters can be found [20.15, 20.16]. To improve the accuracy, three-dimensional models are now used to take into account the different interfacial and vertical parasitic effects [20.17].
Fig. 20.12

Cross Kelvin resistor test structure

Transmission Line Model Test Structures
The transmission line model test structure (TLM) consists of depositing a metal grid pattern of unequal spacing Li between the contacts. This leads to a scaled planar resistor structure. Each resistor changes only by its distance Li between two adjacent contacts, as shown in Fig. 20.13, and it can be expressed by
Then, by plotting the measured resistances as a function of the contact spacing Li, and according to (20.30), the layer sheet resistivity ρs and the contact resistance Rc can be deduced from the slope and from the intercept at Li = 0 respectively, as shown in Fig. 20.14
$$\begin{aligned}\displaystyle\text{Slope}=\frac{\rho_{\mathrm{s}}}{W}\;;\;R_{\mathrm{i}}(\text{intercept})&\displaystyle=2R_{\mathrm{c}}\;;\\ \displaystyle\text{and}\;\left|{L_{\mathrm{i}}(\text{intercept})}\right|&\displaystyle=2L_{\mathrm{T}}\end{aligned}$$
As discussed in Sect. 20.1.2, the most suitable parameter for characterizing a contact is its contact resistivity ( ρc )  or the specific contact resistance ( RcAceff ) , given by
As shown in Fig. 20.8a, for a planar resistor, the effective contact area requires the notion of the transfer length LT. According to (20.20 ), and assuming that the sheet resistance under the contact ρsc is equal to the sheet resistance between the contacts ρs, then LT can be expressed by (20.20).
Fig. 20.13

Transmission line model (TLM) test structure

Fig. 20.14

Determination of the sheet resistivity and characterization of the contact using a TLM test structure

Therefore, the substitution of Rc into (20.32) in (20.30) leads to
Now, extrapolation to Ri = 0 allows us to determine the value of LT. The main advantage of the TLM method is its ability to give two main electrical parameters, the resistivity of the semiconductor contact layer ρs and the contact resistance Rc. However, this is done at the expense of a questionable assumption that the sheet resistance under the contact must be equal to the sheet resistance between the contacts. More on this technique can be found in [20.3].

20.2 Hall Effect

As mentioned before, the resistivity of a semiconductor is not a fundamental material parameter. One can consider the carrier density (n or p) or the carrier mobility ( μ n or μ p  )  to be fundamental or microscopic parameters. For a semiconductor material, the resistivity is related to these two parameters (density and mobility) by (20.2 ). The strength of the Hall effect is to directly determine the sheet carrier density by measuring the voltage generated transversely to the current flow direction in a semiconductor sample when a magnetic field is applied perpendicularly, as shown in Fig. 20.15 a. Together with a resistivity measurement technique such as the four-point probe or the van der Pauw technique, Hall measurements can be used to determine the mobility of a semiconductor sample.
Fig. 20.15

(a) Representation of the Hall effect in an p-type bar-shaped semiconductor. (b) Practical sample geometry: a six-terminal Hall-bar geometry

In modern semiconductor components and circuits, knowledge of these two fundamental parameters n ∕ p and μ n  ∕ μ p is critical. Currently, Hall effect measurements are one of the most commonly used characterization tools in the semiconductor industry and research laboratories. This is not just because of the parameters that can be extracted for use in device modeling or materials characterization, but also because of the quantum Hall effect (QHE ) in condensed matter physics [20.18]. Moreover, in the applied electronics domain, one should note the development of different sensors based on the physical principle of the Hall effect, such as commercial CMOS Hall sensors.

As is very often the case, the development of a characterization technique is related to its cost, simplicity of implementation and ease of use. Since these practical characteristics are satisfied even when specially shaped samples are required, then the Hall effect measurement technique has become a very popular method of characterizing materials.

In this section, we will first present the physical principle of the Hall effect. Then we will show how it can be used to determine the carrier density and mobility. Finally, the influence of the Hall scattering factor will be presented, followed by some practical issues about the implementation of the Hall effect method.

20.2.1 Physical Principles

The Hall effect was discovered by Hall in 1879 [20.19] during an experiment on current transport in a thin metal strip. A small voltage was generated transversely when a magnetic field was applied perpendicularly to the conductor.

The basic principle of this Hall phenomenon is the deviation of some carriers from the current line due to the Lorentz force induced by the presence of a transverse magnetic field. As a consequence, a voltage drop VH is induced transversely to the current flow. This is shown in Fig. 20.15a for a p-type bar-shaped semiconductor, where a constant current flow I x in the x-direction and a magnetic field in the z-direction results in a Lorentz force on the holes. If both holes and electrons are present, they deviate towards the same direction. Thus, the directions of electrical and magnetic fields must be accurately specified.

The Lorentz force is given by the vector relation
where v x is the carrier velocity in the x-direction. Assuming a homogeneous p-type semiconductor
As a consequence, an excess surface electrical charge appears on one side of the sample, and this gives rise to an electric field in the y-direction E y . When the magnetic force FL is balanced by the electric force FEL, then the Hall voltage VH is established, and from a balance between FL and FEL, we get
$$F =F_{\mathrm{L}}+F_{\mathrm{EL}}=-qv_{x}B_{z}+qE_{y}=0\;,$$
$$\text{so }E_{y} =\frac{BI}{qtWp}\;.$$
Also, the Hall voltage VH is given by
So if the magnetic field B and the current I are known, then the measurement of the Hall voltage gives the hole sheet concentration ps from
If the conducting layer thickness t is known, then the bulk hole concentration can be determined (see (20.41 )) and expressed as a function of the Hall coefficient RH, defined as
$$R_{\mathrm{H}} =\frac{tV_{\mathrm{H}}}{BI}$$
$$\text{and }p =\frac{1}{qR_{\mathrm{H}}}$$
Using the same approach for an n-type homogeneous semiconductor material leads to
$$R_{\mathrm{H}} =-\frac{tV_{\mathrm{H}}}{BI}\;,$$
$$\text{and }n =-\frac{1}{qR_{\mathrm{H}}}$$
Now, if the bulk resistivity ρ is known or can be measured at the same time using a known sample such as a Hall bar or van der Pauw structure geometry in zero magnetic field, then the carrier drift mobility can be obtained from
There are two main sample geometries commonly used in Hall effect measurements in order to determine either the carrier sheet density or the carrier concentration if the sample thickness is known, and the mobility. The first one is the van der Pauw structure presented in Sect. 20.1.1. The second one is the Hall bar structure shown in Fig. 20.15b, where the Hall voltage is measured between contacts 2 and 5, and the resistivity is measured using the four-point probes technique presented in Sect. 20.1.1 (contacts 1, 2, 3 and 4). Additional information about the shapes and sizes of Hall structures can be found in [20.20, 20.3, 20.4].

Whatever the geometry used for Hall measurements, one of the most important issues is related to the offset voltage induced by the nonsymmetric positions of the contact. This problem, and also those due to spurious voltages, can be controlled by two sets of measurements, one for a magnetic field in on direction and another for a magnetic field in the opposite direction.

The Hall effect has also been investigated on specific structures, and an interesting example can be found in reference [20.21], where a Hall bar structure was combined with a double-gate n-silicon-on-insulator (SOI ) MOSFET. This was done in order to understand the mobility behavior in ultra-thin devices and to validate the classical drift mobility extraction method based on current–voltage measurements.

In the Hall effect experiment, the measurement of the Hall coefficient RH leads to the direct determination of the carrier concentration and mobility. Moreover, the sign of RH can be used to determine the type of conductivity of the semiconductor sample. If various types of carriers are present, then the expression for RH becomes more complex and approximations in the limit of low and high magnetic field are necessary [20.3, Chap. 8].

We have so far discussed the Hall effect on a uniformly doped substrate or single semiconductor layer deposited on an insulating or semi-insulating substrate. In the case of a semiconductor layer deposited on a semiconducting substrate of opposite doping type, Hall effect measurements can be performed if the space charge region can act as an insulator. In the case of multilayers, the problem is more difficult, but an approximation for transport experiments has been developed for two-layer structures [20.22] and applied to different metal–semiconductor field-effect-transistor (MESFET ) structures, for instance [20.23].

20.2.2 Hall Scattering Factor

The relations presented above are based on an energy-independent scattering mechanism. With this assumption made, the Hall carrier concentration and the Hall mobility are equal to the carrier concentration and the carrier drift mobility. When this assumption is no longer valid, these electrical parameters are different and the Hall scattering factor rH must be taken into account. In this case (20.41), (20.43) and (20.44 ) must be modified as follows
$$p_{\mathrm{H}} =\frac{r_{\mathrm{H}}}{qR_{\mathrm{H}}}=r_{\mathrm{H}}p\;,$$
$$n_{\mathrm{H}} =-\frac{r_{\mathrm{H}}}{qR_{\mathrm{H}}}=r_{\mathrm{H}}n\;,$$
The Hall scattering factor [20.25] is related to the energy dependence of the mean free time between carrier collisions τ ( E ) , and rH is given by
According to theory [20.3], the Hall scattering factor tends to unity in the limit of high magnetic field. Therefore, rH at low magnetic fields can be determined by measuring the Hall coefficient in the limit of both high and low magnetic fields [20.25] using
Depending on the scattering mechanism involved (lattice, ionized or neutral impurity, electron, or phonon scattering), rH is found to vary between 0.6 and 2 [20.26]. However, due to valence band distortion effects, values as low as 0.26 have been found in strained p-type SiGe epilayers [20.27]. Therefore, the Hall carrier concentration and especially the Hall mobility must be distinguished from carrier concentration and carrier drift mobility.
As the different scattering mechanisms have different temperature (T) dependences, then the Hall mobility as function of temperature is often used to separate the different scattering processes. An example is given in Fig. 20.16 for silicon-on-insulator (SOI) films [20.24]. The increase in the mobility between 4 and 45 K, which is given by μ ∝ T2.95, is related to the ionized donor scattering mechanism. The decrease in mobility between 46 and 120 K given by \(\mu\propto T^{-1.55}\) is associated with lattice scattering. However, after 150 K, the rapid decrease in mobility observed, where \(\mu\propto T^{-2.37}\), suggests that other scattering mechanisms as well as the lattice scattering mechanism, such as electron or phonon scattering, must be taken into account.
Fig. 20.16

Hall mobility as a function of temperature on two SOI films. (After [20.24])

20.3 Capacitance–Voltage Measurements

Capacitance–voltage (CV) measurements are normally made on metal-oxide semiconductor (MOS ) or metal-semiconductor (MS ) structures in order to determine important physical and defect information about the insulator and semiconductor materials. For example, high-frequency (HF) and low-frequency (LF ) or quasi-static CV measurements in these structures are used to determine process and material parameters – insulator thickness, doping concentration and profile, density of interface states, oxide charge density, and work function or barrier height. In this section, we describe various CV measurements and how they can be used to provide process parameters as well as valuable information about the quality of the materials. A typical CV curve for a MOS capacitor with an n-type semiconductor is shown in Fig. 20.17. For a MOS capacitor with a p-type substrate, the CV curve be similar to that in Fig. 20.17, but reflected about the y-axis.
Fig. 20.17

Typical CV curve for a MOS capacitor on an n-type substrate. (After [20.28])

20.3.1 Average Doping Density by Maximum–Minimum High-Frequency Capacitance Method

The maximum–minimum high-frequency (HF) capacitance method uses the HF capacitance under strong accumulation ( COX )  and strong inversion \((C_{\text{HF},\min})\) to determine the average doping density [20.29, pp. 406–408]. Note that under strong inversion and at high frequencies, the interface trap capacitance is negligible ( Cit ≈ 0 ) . Under strong inversion, the depletion width ( wmax )  is a maximum and so the high frequency capacitance per unit area \(C_{\text{HF},\min}\) is a minimum, since the minority carriers cannot respond to the high-frequency signal. Since the inversion layer is very thin compared to the depletion layer, then
where εSi is the permittivity of silicon and COX is the gate oxide capacitance per unit area.
At the conditions for wmax, the band bending ψmax is a maximum, and it is
$$\begin{aligned}\displaystyle\psi_{\max}&\displaystyle=2\phi_{\mathrm{B}}+\frac{kT}{q}\ln\left({2\frac{q}{kT}\phi_{\mathrm{B}}-1}\right)\\ \displaystyle&\displaystyle=2\frac{kT}{q}\left\{{\ln\left({\frac{n}{n_{i}}}\right)+\frac{1}{2}\ln\left[{2\ln\left({\frac{n}{n_{i}}}\right)-1}\right]}\right\},\end{aligned}$$
where \(\phi_{\mathrm{B}}=(k_{\mathrm{B}}T/q)\ln(n/n_{i})\) is the shift of the Fermi level from the intrinsic Fermi level \(\phi_{i}=(E_{\mathrm{c}}-E_{v})/2q\) in the bulk of the silicon in the MOS structure due to the doping concentration n, and n i is the thermally generated carrier concentration in silicon. For a uniformly doped sample,
and from (20.50) and (20.52), a relation between the doping concentration n and the measured capacitance can be established [20.29, p. 407] as
$$\begin{aligned}\displaystyle&\displaystyle\frac{n}{\ln\left({\frac{n}{n_{i}}}\right)+\frac{1}{2}\ln\left[{2\ln\left({\frac{n}{n_{i}}}\right)-1}\right]}\\ \displaystyle&\displaystyle\quad=\frac{4kT}{q^{2}\varepsilon_{\mathrm{Si}}}\frac{C_{\mathrm{OX}}^{2}}{\left({\frac{C_{\mathrm{OX}}}{C_{\text{HF},\min}}-1}\right)^{2}}\;.\end{aligned}$$
Equation (20.53) is a transcendental equation in average doping concentration n that can be solved numerically by iteration. Figure 20.18 shows the solutions as function of CHF,min ∕ COX with oxide thickness, and this can be used to obtain the average doping n graphically. Equation (20.53) can be further simplified by neglecting the term \(0.5\ln[2\ln(n/n_{i})-1]\), and assuming COX = CHF,max [20.30]. Also, an approximation of (20.53) for the average doping concentration n in unit cm−3 is obtained in [20.4] and [20.31] for silicon MOS structures at room temperature, and this is given by
$$\begin{aligned}\displaystyle\log_{10}(n)&\displaystyle=30.38759+1.68278\\ \displaystyle&\displaystyle\quad\times\log_{10}(C_{\mathrm{DM}}-0.03177)\\ \displaystyle&\displaystyle\quad\times[\log_{10}(C_{\mathrm{DM}})]^{2}\;,\end{aligned}$$
where the depletion capacitance (per cm2 of area) CDM is defined as
where all capacitances are in units of F ∕ cm2.
Fig. 20.18

Doping concentration n as function of \(C_{\mathrm{HF},\min}/C_{\mathrm{OX}}\) with oxide thickness, based on (20.53). (After [20.29])

20.3.2 Doping Profile by High-Frequency and High–Low Frequency Capacitance Methods

The doping profile in the depletion layer can be obtained [20.29, Sect. 9.4] by assuming that the depletion capacitance per unit area CD and the oxide capacitance per unit area COX are connected in series; that is, that the measured high frequency capacitance CHF is given by
For a particular gate biasing VG of the MOS structure, the depletion thickness w ( VG )  is obtained from CD as
The doping concentration n ( VG )  is given by the slope of the ( 1 ∕ CHF)2 versus VG characteristic, given by
$$n(w)=\frac{-2}{q\varepsilon_{\mathrm{Si}}\frac{\partial}{\partial V_{\mathrm{G}}}\left(\frac{1}{C_{\text{HF}}^{2}}\right)}\;.$$
Note that a plot of 1 ∕ C HF 2 versus VG (Fig. 20.19) can yield important information about the doping profile. The average n is related to the reciprocal of the slope in the linear part of the 1 ∕ C HF 2 versus VG curve, and the intercept with VG at a value of 1 ∕ C OX 2 is equal to the flat-band voltage VFB caused by the fixed surface charge QSS and the gate–semiconductor work function ψMS [20.3, 20.30].
Fig. 20.19

A 1 ∕ C HF 2 versus VG plot [20.30]. The slope of the fitted arrow line is proportional to the average doping, and the arrow points to the flat-band voltage VFB, obtained at the V intercept with 1 ∕ C OX 2 , shown with the second horizontal arrow

Equation (20.58) does not take into account the impact of interface traps, which cause the CV curve to stretch. The traps are slow and do not respond to the high frequency of the test signal, but they do follow the changes in the gate bias. Therefore, ∂ VG must be replaced with ∂ VG0 in (20.58), with ∂ VG0 representing the case when no interface traps are present.

The value of ∂ VG0 can be obtained by comparing high- and low-frequency (quasi-static) CV curves for a MOS structure at the same gate biases VG. Therefore, the ratio \(\partial V_{\mathrm{G0}}/\partial V_{\mathrm{G}}\) can be found at any gate bias VG, since the band-bending is the same for both HF and LF capacitances. In [20.29, Sect. 9.4], it is shown that
$$\frac{\partial V_{\mathrm{G0}}}{\partial V_{\mathrm{G}}}=\frac{C_{\mathrm{OX}}+C_{\mathrm{D}}}{C_{\mathrm{OX}}+C_{\mathrm{D}}+C_{\mathrm{IT}}}=\frac{1-C_{\text{LF}}/C_{\text{OX}}}{1-C_{\text{HF}}/C_{\text{OX}}}\;.$$
In this case (20.58) is modified to
$$n(w)=\frac{-2}{q\varepsilon_{\mathrm{Si}}\frac{\partial}{\partial V_{\mathrm{G}}}\left(\frac{1}{C_{\text{HF}}^{2}}\right)}\frac{1-C_{\mathrm{LF}}/C_{\mathrm{OX}}}{1-C_{\mathrm{HF}}/C_{\mathrm{OX}}}$$
as originally proposed in [20.32] and illustrated in Fig. 20.20a-c. As seen from Fig. 20.20a-c, the stretching of the CV curves due to the interface states induced by stress in Fig. 20.20a-ca causes a disparity in the doping profile in Fig. 20.20a-cb if only the high frequency capacitance is used. The disparity is well-suppressed in Fig. 20.20a-cc by the high–low frequency capacitance measurement, taking into account the stretching of the CV characteristics. Provided that the depletion layer capacitance is measured at a high frequency, the depletion layer width w is still obtained by (20.57).
Fig. 20.20a–c

CV curves and doping profiles of a MOS structure with 145 nm oxide and uniform doping of 1015 cm−3 before and after bias temperature stress [20.32]. (a) Theoretical and (stretched) measured CV curves. (b) Doping profile deduced from only CHF (see (20.58)); (c) Doping profile deduced from both CHF and CLF (see (20.60)). (After [20.32])

Note that the maximum depth wmax (20.52) and the resolution Δ w of the doping profile by means of CV measurements is limited by the maximum band-bending ψmax and the extrinsic Debye length λDebye ,  given by (20.51) and (20.61 ), respectively, and λDebye is
The doping profile obtained in this way is reliable for depths w of between 3λDebye and \(w_{\max}/2\), when the MOS structure is in depletion and weak inversion, but not in accumulation. That is, CLF < 0.7COX as a simple rule. As illustrated in Fig. 20.21 , the range of w values between 3λDebye and equilibrium, obtained via quasi-static CV measurements, cover about half-a-decade. With proper corrections, the lower distance decreases to one Debye length [20.30]. Using nonequilibrium (transient) CV measurements in deep depletion, the profiling can be extended to higher distances by about an order of magnitude, but further limitations can appear due to the high-frequency response of the interface charge, measurement errors, avalanche breakdown in deep depletion, or charge tunneling in highly doped substrates and thin oxides. More details are presented in [20.29].
Fig. 20.21

Limitations on the depth achievable when profiling the doping of silicon MOS structures via CV measurements at room temperature. (After [20.4, p. 86])

20.3.3 Density of Interface States

Interface traps change their charge state depending on whether they are filled or empty. Because interface trap occupancy varies with the slow gate bias, stretching of the CV curves occurs, as illustrated in Fig. 20.20a-c . A quantitative treatment of this stretch-out can be obtained from Gauss’ law as
where QS and QIT are the surface and interface trap charges (per unit area), which are both dependent on the surface band-bending ψS, \(Q_{\mathrm{T}}=Q_{\mathrm{S}}+Q_{\mathrm{IT}}\) is the total charge in the MOS structure, COX is the gate capacitance (per unit area), and VG is the bias applied at the gate of the MOS structure. For simplicity, the (gate metal)-to-(semiconductor bulk) potential ψMS is omitted in (20.62), but in a real structure the constant ψMS must be subtracted from VG. As follows from (20.62), small changes ∂ VG in gate bias cause changes ∂ ψS in the surface potential bending, and the surface CS and interface trap CIT capacitances (both per unit area) can represent QS and QIT, given by
$$C_{\mathrm{OX}}\partial V_{\mathrm{G}}=(C_{\mathrm{OX}}+C_{\mathrm{S}}+C_{\mathrm{IT}})\partial\psi_{\mathrm{S}}\;.$$
CS and CIT are in parallel and in series with the COX, respectively. Therefore, the measured low-frequency capacitance CLF (per unit area) of the MOS structure becomes
$$\begin{aligned}\displaystyle C_{\mathrm{LF}}&\displaystyle=\frac{\partial Q_{\mathrm{T}}}{\partial V_{\mathrm{G}}}=\frac{\partial Q_{\mathrm{T}}}{\partial\psi_{\mathrm{S}}}\frac{\partial\psi_{\mathrm{S}}}{\partial V_{\mathrm{G}}}\\ \displaystyle&\displaystyle=\frac{C_{\mathrm{OX}}\left({C_{\mathrm{S}}+C_{\mathrm{IT}}}\right)}{C_{\mathrm{OX}}+C_{\mathrm{S}}+C_{\mathrm{IT}}}\;.\end{aligned}$$
Equation (20.64) shows that stretch-out in the CV curve can arise due to a non-zero value of CIT, which deviates from the ideal case of CIT = 0.
According to [20.29, p. 142], DIT is the density of interface states per unit area ( cm2 )  and per unit energy (1 eV) in units of \(\mathrm{cm^{-2}{\,}e{\mskip-2.0mu}V^{-1}}\). Since the occupancy of the interface states has a Fermi–Dirac distribution, then upon integrating over the silicon band-gap, the relation between CIT and DIT is
where \(\phi_{\mathrm{B}}=(k_{\mathrm{B}}T/q)\ln(n/n_{i})\) is the shift of the Fermi level from the intrinsic level \(\phi_{\mathrm{i}}=(E_{\mathrm{c}}-E_{\mathrm{v}})/2q\) in the silicon bulk of the MOS structure due to the doping concentration n, and n i is the thermally generated carrier concentration in silicon. Since the derivative of the Fermi–Dirac distribution is a sharply peaking function, then CIT ( ψS )  at particular ψS probes DIT ( φB + ψS )  over a narrow energy range of kBT ∕ q, in which DIT can be assumed to be constant and zero outside this interval. Thus, varying the gate bias VG, and therefore ψS, (20.65) can be used to obtain the density of states DIT at a particular energy shift q ( φB + ψS )  from the silicon intrinsic (mid-gap) energy Ei.

It is evident from (20.64) and (20.65) that the experimental values for DIT can be obtained only when CIT, and ψS are determined from CV measurements. The simplest way to determine φB is to get the average doping density n using the maximum–minimum high-frequency capacitance method (see (20.53) and Fig. 20.18), or to use the values of n from doping profiles at 0.9 wmax – see (20.59) [20.30]. Either the high-frequency or the low-frequency C − V measurement can be used to obtain CIT, but it is necessary to calculate CS as function of ψS, which makes it difficult to process the experimental data.

The most suitable technique for experimentally determining DIT is the combined high–low frequency capacitance method [20.29, Sect. 8.2.4, p. 332]. The interface traps respond to the measurement of low–frequency capacitance CLF, whereas they do not respond to the measurement of the high-frequency measurement CHF. Therefore, CIT can be obtained from measurements by subtracting CHF from CLF, given by
Denoting \(\Updelta C=C_{\mathrm{LF}}-C_{\mathrm{HF}}\), the substitution of (20.66) into (20.65 ) provides a direct estimate of DIT from CV measurements (see also [20.3, p. 371]) as
$$D_{\mathrm{IT}}=\frac{\Updelta C}{q}\left(1-\frac{C_{\mathrm{LF}}}{C_{\mathrm{OX}}}\right)^{-1}\left(1-\frac{C_{\mathrm{HF}}}{C_{\mathrm{OX}}}\right)^{-1}$$
Note that the combined high–low frequency capacitance method provides CIT and DIT as function of gate bias VG. However, if DIT needs to be plotted as a function of the position in the energy band-gap, the surface band-bending ψS must also be determined as function of gate bias VG, as follows from (20.65).
There are several ways to obtain the relation between ψS and VG. One way is to create a theoretical plot of CHF versus ψS and then, for any choice of CHF, a pair of values for ψS and VG is found [20.29, p. 327]. This method is relatively simple if the doping concentration n in the silicon is uniform and known, because the high-frequency silicon surface capacitance CS under depletion and accumulation is a simple function of the band-bending ψS, and the flat-band capacitance CFB [20.29, pp. 84, 97, 164] is given by
$$C_{\mathrm{FB}} =\frac{\varepsilon_{\mathrm{Si}}}{\lambda_{\mathrm{Debye}}}=\sqrt{\frac{\varepsilon_{\mathrm{Si}}q^{2}n}{k_{\mathrm{B}}T}}$$
$$C_{\mathrm{S}}(\psi_{\mathrm{S}}) \approx\left\{\begin{array}[]{l}\frac{C_{\mathrm{FB}}}{\sqrt{2}}\frac{\exp\left(\frac{q\psi_{\mathrm{S}}}{k_{\mathrm{B}}T}\right)-1}{\sqrt{\exp\left(\frac{q\psi_{\mathrm{S}}}{k_{\mathrm{B}}T}\right)-\frac{q\psi_{\mathrm{S}}}{k_{\mathrm{B}}T}-1}}\;,\\ \;\quad\quad\psi_{\mathrm{S}}> 0\;\text{in accumulation}\\ C_{\mathrm{FB}},\psi_{\mathrm{S}}=0\;\text{at flat band,}\\ \frac{C_{\mathrm{FB}}}{\sqrt{2}}\frac{1-\exp\left(\frac{q\psi_{\mathrm{S}}}{k_{\mathrm{B}}T}\right)}{\sqrt{\exp\left(\frac{q\psi_{\mathrm{S}}}{k_{\mathrm{B}}T}\right)-\frac{q\psi_{\mathrm{S}}}{k_{\mathrm{B}}T}-1}}\;,\\ \;\quad\quad\psi_{\mathrm{S}}<0\;\text{in depletion}\;.\end{array}\right.$$
Since CS is in series with COX, then the theoretical CHF is obtained as a function of the band-bending ψS by
For a uniformly doped silicon with SiO2 as the insulator, the ratio CHF ( VFB )  ∕ COX at gate bias for flat-band conditions is given [20.3, p. 349] by
where tox is the oxide thickness ( cm ) , n is the doping ( cm−3 ) , and the T is the temperature ( K ) .

It was demonstrated in [20.29] that the method of using a theoretical plot to obtain the relation between ψS and VG works well in the case of uniformly doped silicon even if only high-frequency CV measurements are used to obtain the density of states; that is, the 1 ∕ C HF 2 versus VG plot is almost a straight line. However, with substrates that are not uniformly doped, the method is inconvenient because the corrections in (20.68) and (20.69) are difficult to implement. Therefore, in practice, a method based on low-frequency CV measurement is preferred [20.30].

Low-frequency CV measurement was first used to obtain the relation between ψS and VG [20.34]. This method is based on the integration of (20.66) from an initial gate bias VG0, arbitrarily chosen either under strong accumulation or strong inversion, to the desired VG at which the band-bending ψS ( VG )  is to be obtained. Since CIT is part of (20.66), then the low-frequency CV curve [20.29, p. 93] is integrated as
The value of ψS0 is selected such that ψS ( VFB )  = 0 when integrating from VG0 to the flat-band gate voltage VFB. In this case, VFB is usually obtained beforehand from the point of V-intercept with 1 ∕ C OX 2 when extrapolating the linear part of the 1 ∕ C HF 2 versus VG curve toward the VG axis (Fig. 20.19). After determining ψS0, (20.72) provides the relation between ψS and VG. Thus, the density of states DIT obtained from (20.67) as function of VG using the combined high–low frequency capacitance method can be plotted against the position of DIT in the silicon band gap, as given by (20.65). High and low frequency CV measurements can therefore be used to plot the data, as illustrated in the insert of Fig. 20.22.
Fig. 20.22

Results from the combined high–low frequency capacitance method [20.33]. (a) High-frequency CV curve; (b) low-frequency CV curve. The energy profile for the density of interface states DIT is shown in the inset, as calculated by (20.65), (20.67) and (20.72)

Overall, many different techniques are used to determine the density of states DIT (Fig. 20.23 ). For some of these techniques, the ability to sense the energy position of DIT in the band-gap of silicon is summarized in [20.3]. Most of them use CV measurements, but others are based on IV measurements taken during the subthreshold operation of MOS transistors, deep-level transient spectroscopy (DLTS ), charge pumping (CP ) in a three-terminal MOS structure, cryogenic temperature measurements, and so on. Each technique has its strengths and weaknesses, which are discussed in [20.3, 20.35].
Fig. 20.23

Energy ranges in the silicon band-gap of a p-type substrate over which the density of interface traps can be determined using various measurement methods and characterization techniques. (After [20.3, p. 104])

In the methods discussed above, it has been assumed that the gate bias VG varies slowly with time, 20–50 mV ∕ s, and that the MOS structure is in equilibrium; that is, the minority carriers are generated and the inversion layer is readily formed in the MOS structure when VG is above the threshold. However, the time constant for minority carrier generation is high in silicon (≈ 0.1 s or more), and it is possible to use nonequilibrium high-frequency CV measurements to further analyze the properties of the MOS structure. Some applications of these methods are presented later.

20.4 Current–Voltage Measurements

20.4.1 IV Measurements on a Simple Diode

Current–voltage measurements of mainstream semiconductor devices are perhaps the simplest and most routine measurements performed, and they can provide valuable information about the quality of materials used. For example, if we consider the IV characteristics of a p-n diode structure, the source–substrate or drain–substrate junctions can provide useful information on the quality of the junction, such as whether defects are present (they give rise to generation–recombination currents or large parasitic resistances for the contacts at the source, drain or substrate terminals). This is easily seen from the current–voltage relation given by the sum of the diffusion ( IDIFF )  and recombination ( IGR )  currents
$$\begin{aligned}\displaystyle I_{\mathrm{D}}&\displaystyle=I_{\mathrm{DIFF}}+I_{\mathrm{GR}}=I_{\mathrm{D0}}\left[\exp\left(\frac{eV_{\mathrm{D}}}{nk_{\mathrm{B}}T}\right)-1\right]\\ \displaystyle&\displaystyle\quad+I_{\mathrm{GR0}}\exp\left(\frac{eV_{\mathrm{D}}}{2k_{\mathrm{B}}T}\right)\end{aligned}$$
where ID0 and IGRO are the zero-bias diffusion and recombination currents respectively, n is an ideality factor (typically 1), and VD is the voltage across the intrinsic diode, which is given by
For (20.73), a plot of ln ( ID )  versus VD allows us to separate out the diffusion and the recombination current components. From (20.73) and (20.74), we can also use the diode’s IV characteristics to determine the parasitic resistance in series with the intrinsic diode, as described in detail in [20.36]. In most cases, this Rparasitic is dominated by the contact resistance.

20.4.2 IV Measurements on a Simple MOSFET

Simple current–voltage measurements – drain current versus gate voltage ( IDSVGS ) , and IDS versus drain voltage (VDS )  – are routinely taken on MOSFETs in order to study their electrical characteristics; however, these can also be used to obtain useful information on the quality of the semiconductor, contacts, oxide and semiconductor–oxide interface. For example, the IDS − VGS characteristics at very small VDS biases (linear region of operation) for a set of test transistors of fixed channel width and different channel lengths is often used to extract parameters such as the threshold voltage ( VT ) , the transconductance ( gm ) , the intrinsic mobility ( μo )  and the mobility degradation coefficients θ0 and η, the parasitic source ( RS )  and the drain resistances ( RD )  in series with the intrinsic channel, the channel length reduction ΔL, the output conductance ( gDS )  and the subthreshold slope (S) [20.37].

These parameters are required for modeling and they directly impact the device’s performance. However, some of these parameters can also be used to assess the quality of the silicon–silicon dioxide (Si–SiO2) interface [20.38, 20.40]. For example, interface states at the Si–SiO2 interface can change the threshold voltage, the subthreshold slope and the mobility, all of which will impact on the drain–source ( IDS )  current flowing through the device. Here, we look at one parameter in more detail – the subthreshold slope S in mV (of VGS)/decade (of IDS).

First, the interface trap density ( DIT )  can be determined from a semi-log plot of IDS − VGS characteristics at very low drain biases, as shown in Fig. 20.24 . We start with the expression for the subthreshold slope
in which
DIT can then be calculated from
once CIT is determined from (20.75). In fact, a recent comparison in [20.41] of the interface trap densities extracted from capacitance, subthreshold and charge pumping measurements produced similar results, demonstrating that simple and fast IV measurements based on the subthreshold technique can provide useful information on the Si–SiO2 quality.
Fig. 20.24

Typical subthreshold characteristics of a MOSFET. The interface state density can be extracted from S

20.4.3 Floating Gate Measurements

The floating gate technique is another simple IV measurement in which the evolution of the drain current IDS is monitored after the gate bias has been removed. It has been shown to be particularly useful when monitoring early-mode hot-carrier activity in MOS transistors [20.39, 20.41]. In this measurement, we first check the oxide quality by biasing the transistor in the strong linear region (very low VDS and a VGS well above VT), and then lift the gate voltage probe so that VGS = 0 V and measure the evolution of IDS with time. For a high-quality gate and spacer oxide, IDS remains constant for a long time, indicating that there is negligible carrier injection across the gate oxide through Fowler–Nordheim tunneling or other leakage mechanisms.

A second precaution is to have a dry or inert gas such as nitrogen flowing over the chip to reduce the possibility of other leakage mechanisms such as that from water vapor. The measurement set-up for this experiment is shown in Fig. 20.25. The evolution of the floating gate current over several cycles with the gate voltage applied and then removed is shown in Fig. 20.26. The biasing voltages and time at which the gate is floated are also given in Fig. 20.26a. For this experiment, a biasing condition of VGS ≈ VDS was chosen for a high-impact ionization-induced gate current, but a lower-than-maximum electron injection situation was used for the initial biasing condition.
Fig. 20.25

Schematic diagram showing the set-up used for floating gate measurements. The area where charge is trapped after hot electrons are applied is shown

Fig. 20.26

(a) Evolution of the drain current over five floating gate cycles. Biasing conditions were chosen to maximize hot-electron gate currents. Note that the maximum drop in drain current occurs after the first floating gate cycle. (b) Extracted gate currents using (20.78) and the measurements in (a). As with the drain current, the maximum change in gate current occurs between floating gate cycles 1 and 2. The shift in the peak of the gate current is explained in [20.38, 20.39]

From the evolution of IDS and the IDS − VGS characteristics of a virgin (not intentionally stressed) transistor at the same VDS as the floating gate measurements, and from measurements of the total capacitance associated with the gate ( CG ) , the gate current ( IG )  evolution after each floating gate cycle can be determined using
This IG − VGS evolution is shown in Fig. 20.26 b. An ancillary benefit of the floating gate technique is that very small gate currents (in the fA range or even smaller) can be easily determined by measuring much larger drain currents using, for example, a semiconductor parameter analyzer. The reason for this is that the gate current is not directly measured in this technique – it is determined from IDS − VGS and (20.78). Also, the change in the floating gate current after the first few cycles can be used to monitor for early mode failure after statistical evaluation.

20.5 Charge Pumping

Charge pumping (CP) is another electrical technique that is well suited to studying semiconductor–insulator interfaces in MOSFETs [20.42, 20.43, 20.44, 20.45, 20.46, 20.47]. There are several versions of the CP technique: spatial profiling CP [20.43, 20.44, 20.45, 20.46, 20.47], energy profiling CP [20.48], and, more recently, new CP techniques [20.49] that permit the determination of both interface states ( NIT )  and oxide traps ( NOT )  away from the interface and inside the oxide. The charge pumping technique is more complicated than either of the IV or floating gate methods. However, it is a very powerful technique for assessing interface quality and it works well even with very small transistor geometries and very thin gate oxides, where tunneling can be a problem.

The charge pumping technique was first used in 1969 [20.50] to measure the interface traps at Si − SiO2 interface . Since then, there have been numerous publications with enhancements, refinements and applications of the technique to a variety of semiconductor–insulator interfacial studies. In the basic charge pumping experiment, the gate of an NMOST (for example) is pulsed from a low value ( VL )  when the device is in accumulation to a high value ( VH )  when the device is in inversion. This results in the filling of traps between EF,ACC (corresponding to VL) and EF,INV (corresponding to VH) with holes and electrons, respectively. When pulsing the gate between accumulation at VL and inversion at VH, a current flows due to the repetitive recombination at the interface traps of minority carriers from the source and drain junctions with majority carriers from the substrate. This current is termed the charge pumping current, and it was found to be proportional to the frequency of the gate pulse, the gate area and the interface state density. Its sensitivity is better than \({\mathrm{10^{9}}}\,{\mathrm{cm^{-2}{\,}e{\mskip-2.0mu}V^{-1}}}\). In the traditional CP experiment shown in Fig. 20.27, but with \(\Updelta V_{\mathrm{S}}=|V_{\mathrm{D}}-V_{\mathrm{S}}|={\mathrm{0}}\,{\mathrm{V}}\), the gate G is connected to a pulse generator, a reverse bias VR or no bias is applied to both sources S and drain D terminals, and the charge pumping current flowing in the substrate terminal, ICP, is measured. To generate a typical charge pumping curve (as shown in the top part of Fig. 20.28), the base level of the pulse is varied, taking the transistor from below flat-band to above surface inversion conditions, as shown in the bottom part of Fig. 20.28.
Fig. 20.27

Example of spatial profiling charge-pumping set-up used when the source and drain biases are slightly different

Fig. 20.28

Demonstration of how the CP curve is generated by varying the base level of the pulse so that the entire pulse is between VFB and VT

In the traditional CP experiment, the charge pumping current ICP is given by
$$I_{\mathrm{CP}}=qA_{\mathrm{GATE}}\overline{D_{\mathrm{IT}}}\Updelta E\;,$$
$$\Updelta E=\left({E_{\mathrm{F,INV}}-E_{\mathrm{F,ACC}}}\right).$$
This expression assumes that the electrical and physical channel lengths are the same. However, for short channel devices, this assumption results in an error. Therefore, a more accurate expression is
$$I_{\mathrm{CP}} =q\,f\,W\int_{x_{\mathrm{s}}}^{x_{\mathrm{d}}}{N_{\mathrm{IT}}(x)(q\Updelta\psi_{\mathrm{SO}})}$$
$$x_{\mathrm{d}} =L-\sqrt{\frac{2\varepsilon_{\mathrm{Si}}}{qN}}\left({\sqrt{V_{\mathrm{D}}+\psi_{\mathrm{S}}}-\sqrt{\psi_{\mathrm{S}}}}\right).$$
The interface state density at the edge of the drain depletion region (NIT ( xd ) ) is given by
When performing spatial profiling CP experiments, some precautions are required. The first is that a voltage difference ΔVS between VD and VS that is too small results in a difference in ICP that is too small as well, and hence a large error in NIT ( x ) , as indicated from (20.83). On the other hand, values of ΔVS that are too large result in a ID that is too high and hence more substrate current IB. This current IB can interfere with ICP if ΔVS is large or if L is very short, resulting in a large error in NIT ( x ) . The range 50–100 mV for ΔVS seems to be a good compromise for the devices investigated in [20.43, 20.44]. Experimental results for spatial profiling CP measurements indicate that NIT ( x )  peaks near S∕D edges. However, after normal mode stress, NIT ( x )  only increases near D. This is shown in Fig. 20.29. More details about charge pumping can be found in a recent review [20.51].
Fig. 20.29

Spatial interface state distribution over the channel in a 1 μm-long device. The stress was applied for 2 h at VDS = 5 V and VGS = 2.4 V

20.6 Low-Frequency Noise

20.6.1 Introduction

Low-frequency noise (LFN ) spectroscopy requires very good experimental skills in the use of low-noise instrumentation as well as grounding and shielding techniques. Other special considerations are also required, which are discussed later. Although it is time-consuming to perform, it has been widely used to probe microscopic electrical transport in semiconductors and metals. LFN is very sensitive to defects in materials and devices, and large differences in LFN characteristics can be observed in devices with identical electrical current–voltage characteristics. This is mainly because electrical IV measurements only probe the average or macroscopic transport in devices and so are not as sensitive to defects as LFN. Due to its sensitivity to defects, traps or generation–recombination centers, LFN has been proposed as a good tool for predicting device reliability. For example, LFN has been used to predict the reliabilities of metal films [20.52], and has been used in processing steps that produce photodetectors with better performance [20.53, 20.54]. LFN noise is sensitive to both bulk and surface defects or contaminants of a material.

Using low-frequency noise spectroscopy and biasing the transistor in saturation, we can spatially profile the defect density near the drain and source terminals for devices in normal and reverse modes of operation [20.55]. Low-frequency noise in the linear region also allows us to extract the average defect density over the entire channel region at the silicon–silicon dioxide interface [20.56, 20.57]. Noise experiments were performed on small-geometry polysilicon emitter bipolar transistors to investigate the number of interface states in the thin interfacial oxide layer between the monocrystalline and polycrystalline silicon [20.58, 20.59, 20.60, 20.61, 20.62, 20.63, 20.64, 20.65, 20.66, 20.67, 20.68]. Recent experiments using body or substrate bias ( VB )  in a MOS transistor allowed us to look at the contribution of bulk defects (defects away from the silicon–silicon dioxide interface) and their contribution to device noise [20.69, 20.70, 20.71]. This is important since substrate biasing has been proposed as a means to cleverly manage power dissipation and speed in emerging circuits and systems [20.72].

We will discuss how low-frequency noise (LFN) spectroscopy can be applied to the interfacial oxide layer between the mono-silicon and polysilicon emitter in bipolar junction transistors (BJT s) here. The experimental system shown in Fig. 20.30 is used for LFN measurements of field-effect transistors (FET s); the same system can also be used for BJTs.
Fig. 20.30

System for measuring low-frequency noise. In this diagram, the device under test is any field-effect or thin-film transistor

As mentioned before, special attention must be paid to grounding and shielding in LFN measurements, as this is crucial to minimizing the effects of experimental and environmental noise sources on the device under test (DUT ). Because electric power supplies are noisy, especially at 60 Hz (in North America) and its harmonics, and this noise can dominate the noise of the DUT, batteries are often used to supply the voltage. Metal film resistors are the preferred means of changing the biasing conditions, because of their better low-noise characteristics compared to carbon resistors, for example.

With these experimental precautions taken, the noise signal from the transistor might still be too low to be directly measured using a spectrum or signal analyzer. Therefore, a low-noise voltage or current amplifier, whose input noise sources are lower than that of the noise signal, is used to boost the noise signal. In addition, other instruments might be used to measure currents or voltages, or to display the waveforms (as shown in Fig. 20.30 ). An example of a low-frequency noise characterization system that we have used to study the noise in thin film polymer transistors is shown in Fig. 20.30. Note that LFN measurements are time intensive because a large number of averages are required for smooth spectra. Also, in noise measurements, the power spectrum densities S V and S I for the noise voltages and currents are measured, in units V2 ∕ Hz and A2 ∕ Hz, respectively.

20.6.2 Noise from the Interfacial Oxide Layer

Here we present some sample results and show how low-frequency noise spectra in ultrasmall devices can be used to estimate the oxide trap density. Generally, the low-frequency noise spectra of polysilicon emitter (PE) BJTs are made up of 1 ∕ f noise, generation–recombination (g–r) noise and shot noise sources. In the case of the base current, the noise spectra can be modeled as
$$S_{I_{\mathrm{B}}}=\frac{K_{\mathrm{F}}I_{\mathrm{B}}^{A_{\mathrm{F}}}}{f}+\sum_{i=1}^{n}\frac{B_{i}\tau_{i}}{1+(2\uppi f\tau_{i})^{2}}+2qI_{\mathrm{B}}\;,$$
where the symbols have their usual meanings, see [20.68] for example.
As described in [20.63, 20.64, 20.65, 20.66, 20.67, 20.68], the LFN in PE BJTs originates from the thin layer of oxide between the monocrystalline and polycrystalline silicon emitter. The defects at this interface may be dangling oxygen bonds, oxygen vacancies, interface states or oxide traps [20.63]. Devices with large emitter areas have many traps, and these produce generation–recombination noise which produce 1 ∕ f noise when added. This is schematically shown in Fig. 20.31.
Fig. 20.31

Schematic representation of a large-area PE-BJT with many traps distributed uniformly across the band gap and the emitter area, and with a \(g(\tau)=1/\tau\) distribution for the time constant. The resulting spectrum is 1 ∕ f noise

As the device area is reduced, and assuming a constant trap density (which is normally true for devices on the same wafer), then there are fewer traps in the interfacial oxide layer for smaller area devices. In this case, the spectral density of the noise changes and it gains characteristic bumps associated with resolvable g–r noise components. This is schematically shown in Fig. 20.32.
Fig. 20.32

Schematic representation of a medium-area PE-BJT (  ≈ 0.5 μm2 )  with a few traps. Note that g–r bumps appear for each trap since there are only a few traps

In very small devices with only a single trap, for example, the noise spectrum changes dramatically; only g–r noise is observed in the frequency domain along with a random telegraph signal (RTS ) in the time domain. This is schematically shown in Fig. 20.33. Real experimental results are shown for three sizes of transistors (2.4, 0.64 and 0.16 μm2) in Fig. 20.34 . Here, one can see how 1 ∕ f noise is made up of g–r spectra as the emitter geometries are scaled to smaller and smaller values. For the PE BJT with an emitter area of 0.16 μm2, a lower bound of ≈ 109 cm2 can be approximated for the oxide trap density. Similar results have been obtained for MOSFETs [20.73].
Fig. 20.33

Schematic representation of a small-area PE-BJT (  ≈ 0.1 μm2 )  with one trap. Note that (a) a single RTS and (b) g–r spectrum appear because there is only one trap

Fig. 20.34

Experimental results for low-frequency noise spectra from sets of large-, medium- and small-area PE-BJTs. In all cases, the average spectrum is 1 ∕ f noise and the relative magnitude of the 1 ∕ f noise is the same; that is, the area of KF ×  is the same for the three sets of transistors. (After [20.59, 20.60, 20.61, 20.62])

20.6.3 Impedance Considerations During Noise Measurement

Two basic circuits can be employed when measuring the low-frequency noise (LFN) in a device. These configurations are sketched in Fig. 20.35a,b . In voltage noise measurement (Fig. 20.35a,ba), a low-noise preamplifier senses the voltage across the device, and this signal is sent to a spectrum analyzer or a fast Fourier transform (FFT ) analyzer. In current noise measurements (Fig. 20.35a,bb), the low-noise preamplifier senses the current through the device, converts it into a voltage, and forwards the voltage to a FFT or spectrum analyzer.
Fig. 20.35a,b

Basic circuits used to measure the low-frequency noise (LFN) in a device (DUT). (a) Voltage noise measurement; (b) current noise measurement

In principle, both configurations can be used for LFN measurement, but the impact of the nonideality of the amplifier (such as the input impedance, noise voltage and current) changes when the device impedance changes. Also, the noise from the bias source varies with each measurement set-up.

The noise equivalent circuit used for voltage measurement is shown in Fig. 20.36. The noise from the amplifier is represented by the input-referred noise voltage ( SVn )  and noise current ( SIn )  sources. The noise voltage from the bias is represented by SV0. The impedance of the bias source is R0, whereas the input impedance of the amplifier is neglected, since it is usually very high compared to R0. The impedance of DUT is rd. The noise current SId of the device that can be measured, assuming that the noise voltage at the input of the amplifier SVm = SIdr d 2 . However, the amplifier sees a different level of SVm, given by
$$\begin{aligned}\displaystyle S_{V\mathrm{m}}&\displaystyle=\frac{S_{\mathrm{OUT}}}{A^{2}}=S_{V0}\left(\frac{r_{\mathrm{d}}}{r_{\mathrm{d}}+R_{0}}\right)^{2}\\ \displaystyle&\displaystyle\quad+S_{V{\mathrm{n}}}+(S_{I\mathrm{I}}+S_{I\mathrm{I}})Z^{2}\end{aligned}$$
and A is the voltage gain of the amplifier. Therefore, the estimated value for SId is
The uncertainty in (20.87) is
$$\frac{\Updelta S_{I\mathrm{d}}}{S_{I\mathrm{d}}}=\frac{\Updelta S_{V\mathrm{n}}}{S_{V\mathrm{m}}}+\frac{\Updelta S_{V\mathrm{0}}}{S_{V\mathrm{m}}}\left({\frac{Z}{R_{0}}}\right)^{2}+\frac{\Updelta S_{I\mathrm{n}}}{S_{V\mathrm{m}}}Z^{2}$$
where ΔS ≤ S denotes the uncertainty in each noise source. As seen from (20.88 ), the impact of the bias source noise ΔSV0 and the input current noise ΔSIn can be reduced if the impedance of the measurement circuit Z is low and the ratio rd ∕ R0 is kept much less than 1; in other words, the voltage noise measurement is more appropriate for low-impedance devices, such as diodes at forward biasing, and the noise floor of the measurement is limited by the input-referred voltage noise \(S_{V_{\mathrm{n}}}\) of the amplifier.
Fig. 20.36

Noise equivalent circuit for voltage noise measurements

For the other (dual) case, current noise measurement, the noise equivalent circuit is shown in Fig. 20.37. The corresponding equations for the measured noise current SIm, Z, the device noise SId, and the uncertainty, respectively, are given by (20.8920.92) below
$$\begin{aligned}\displaystyle S_{I\mathrm{m}}&\displaystyle=\frac{S_{\mathrm{OUT}}}{R^{2}}=\frac{S_{V0}}{\left({r_{\mathrm{d}}+R_{0}}\right)^{2}}S_{I\mathrm{n}}+\frac{S_{V\mathrm{n}}}{Z^{2}}\\ \displaystyle&\displaystyle\quad+S_{I\mathrm{d}}\left({\frac{r_{\mathrm{d}}}{r_{\mathrm{d}}+R_{0}}}\right)^{2}\end{aligned}$$
$$Z =\left({r_{\mathrm{d}}+R_{0}}\right)//R=\left({\frac{1}{R}+\frac{1}{r_{\mathrm{d}}+R_{0}}}\right)^{-1}$$
$$\begin{aligned}\displaystyle S_{I\mathrm{d}}&\displaystyle=(S_{I\mathrm{m}}-S_{I\mathrm{n}})\left(1+\frac{R_{0}}{r_{\mathrm{d}}}\right)^{2}-\frac{S_{V0}}{r_{\mathrm{d}}^{2}}\\ \displaystyle&\displaystyle\quad-\frac{S_{V\mathrm{n}}}{Z^{2}}\left(1+\frac{R_{0}}{r_{\mathrm{d}}}\right)^{2}\end{aligned}$$
$$\frac{\Updelta S_{I\mathrm{d}}}{S_{I\mathrm{d}}} =\frac{\Updelta S_{I\mathrm{n}}}{S_{I\mathrm{m}}}+\frac{\Updelta S_{V0}}{S_{I\mathrm{m}}}\frac{1}{\left({r_{\mathrm{d}}+R_{0}}\right)^{2}}+\frac{\Updelta S_{V\mathrm{n}}}{Z^{2}S_{I\mathrm{m}}}$$
As expected from duality, it is apparent from (20.92 ) that the impact of the bias source noise ΔSV0 and the input voltage noise ΔSIn can be reduced if the impedance of the measurement circuit Z and ( rd + R0 )  are both high; in other words, the current noise measurement is more appropriate for high-impedance devices, such as diodes at reverse biasing, and the noise floor of the measurement is limited by the input-referred current noise \(S_{I_{\mathrm{n}}}\) of the amplifier.
Fig. 20.37

Noise equivalent circuit of the current noise measurement

This analysis above demonstrates that the choice of the measurement configuration follows our expectation that voltage should be measured in low-impedance devices and current in high-impedance devices. Also, the noise floor limiting parameter of the preamplifier is of the same type as the type of measurement; that is, input-referred noise voltage for voltage noise measurement and input-referred noise current for current noise measurement. Note that there is a trade-off between the voltage and current noise in amplifiers, which implies that the measurement configuration – either voltage or current measurement – should also be carefully selected with respect to the impedance of the device under test. In addition, four-point connection can be used to measure the noise in very low impedance devices ( rd < 100 ) . These and other considerations for low-frequency noise instrumentation are discussed in many papers, for example [20.74, 20.75, 20.76].

20.7 Deep-Level Transient Spectroscopy

Deep-level transient spectroscopy (DLTS) is a fairly complicated electrical characterization technique where the temperature is varied in large range from cryogenic temperatures (  < 80 K )  to well above room temperature (  > 400 K ) . However, it is a powerful and versatile technique for investigating deep-level defects and it also gives accurate values for the capture cross-sections of defects. There are several DLTS techniques and [20.77, 20.78] provide recent reviews of the subject. In DLTS, the semiconductor device or junction is pulsed with an appropriate signal, and the resulting transient (such as capacitance, voltage or current) is monitored at different temperatures. Using these recorded transients at different temperatures, it is possible to generate a spectrum with peaks, each of which is associated with a deep level. The heights of the peaks are proportional to the defect density.

Here, we will focus on a new version of DLTS: the constant resistance (CR) DLTS technique [20.79, 20.80, 20.81]. We were able to accurately investigate bulk defects in a variety of test structures with CR-DLTS. Using body bias in a MOS transistor, we were able to distinguish interfacial and bulk defects that are important for different applications. For example, interfacial defects are important for electronic applications, and bulk defects are important for imaging or radiation detection applications. Examples of results from DLTS studies with and without body bias will be discussed.

CR-DLTS is well-suited to investigations of electrically active point defects that are responsible for the creation of deep levels in the semiconductor band-gap. CR-DLTS can also be used to distinguish bulk traps and interface traps in MOSFETs.

A conventional DLTS system is shown schematically in Fig. 20.38. In DLTS, an excitation pulse is applied to the sample to fill all of the traps and then the pulsing is stopped. The next step is to detect the transient signal from the sample due to charge emission from the traps. The right side of Fig. 20.38 shows capacitance transients at eight different temperatures. By selecting a time window from t1 to t2, and then plotting [ C ( t1 )  − C ( t2 )  ]  as a function of temperature, a DLTS spectrum with a characteristic peak is obtained as shown in the bottom of Fig. 20.38.
Fig. 20.38

Schematic representation of a conventional DLTS system. The time scans from which the DLTS temperature spectrum is obtained are shown on the right

This peak is a signature from a specific defect level. To determine the properties of the defect (its energy level and capture cross-section), the time window \((\tau=t_{2}-t_{1})\) is changed. In this case, different DLTS spectra are obtained at different temperatures. Using the time difference τ and the temperatures at which the peaks occur, Arrhenius plots are constructed in order to determine the defect energy level and its capture cross-section. Examples of DLTS spectra and Arrhenius plots associateed with CR-DLTS are presented later (in Fig. 20.40).
Fig. 20.39

Block diagram representation of the CR-DLTS system

Fig. 20.40

(a) CR-DLTS spectra of a 50 μm × 20 μm MOSFET damaged with \({\mathrm{2.7\times 10^{9}}}\,{\mathrm{proton/cm^{2}}}\). (b) Arrhenius plot derived from the CR-DLTS spectra, showing the energies of the five traps E1–E5. (After [20.80, 20.83])

A block representation of the CR-DLTS system is shown in Fig. 20.39 . More details can be found in [20.79, 20.80, 20.81, 20.82, 20.83]. A discussion of the signal processing and averaging techniques used with this DLTS technique can be found in [20.82]. Here, the gate bias voltage of the field-effect transistor is adjusted using a feedback circuit so that the resistance corresponding to the source–drain conductance matches that of a reference resistor Rref, which is typically around 1 MΩ. The voltage transient due to the change in occupancy of the traps appears as a compensation voltage on the gate. This voltage change can be regarded as a threshold voltage change because the flat-band voltage of the device changes when the occupancy of the traps change. More details on how this change in the threshold is related to the traps can be found in [20.77, 20.79, 20.81].

Some important advantages of the CR DLTS technique are that the surface mobility of the MOS transistors does not need to be high, and that it is theoretically independent of the gate area of the transistor. This is expected, since the small amount of charge trapped beneath the gate must be balanced by a correction voltage applied across a relatively small gate–substrate capacitance.

Figure 20.40a shows six DLTS spectra for a junction field-effect transistor (JFET ) damaged with \({\mathrm{2.7\times 10^{9}}}\,{\mathrm{protons/cm^{2}}}\) [20.79, 20.81] with six selected rate windows. Using the temperatures at which the peaks occur and the rate windows, Arrhenius plots can be constructed as shown in Fig. 20.40b, where the energies of five electron trap levels below the conduction band are also indicated. For the five traps, the extracted capture cross sections were \({\mathrm{4.6\times 10^{-15}}}\,{\mathrm{cm^{2}}}\) (E1), \({\mathrm{6.3\times 10^{-15}}}\,{\mathrm{cm^{2}}}\) (E2), \({\mathrm{1.2\times 10^{-16}}}\,{\mathrm{cm^{2}}}\) (E3), \({\mathrm{8.5\times 10^{-16}}}\,{\mathrm{cm^{2}}}\) (E4) and \({\mathrm{3.4\times 10^{-15}}}\,{\mathrm{cm^{2}}}\) (E5).

Figure 20.41 shows CR-DLTS spectra as the source–body bias voltage is varied. The scans with a body bias of −1 V are lower in magnitude than those without substrate bias, except for the peak associated with the hole trap at 0.13 eV above the valence band [20.81]. When the reverse substrate bias is increased, the gate control of the space charge region near the channel decreases, meaning that fewer interface traps participate in the capture and emission of charges. However, the increased reverse substrate bias results in an increased space charge region in the silicon beneath the gate, so more bulk deep levels can participate in the capture and emission processes. This explains the increased deep-level peak (below 75 K) when −1 V is applied to the body. These differences between the CR-DLTS spectra demonstrate the ability to distinguish bulk traps from surface traps when the substrate bias of the MOSFET is varied.
Fig. 20.41

Effect of body bias on CR-DLTS spectra. The body bias affects the surface and bulk traps in different ways



The authors are very grateful to Drs. O. Marinov and D. Landheer for their careful review of the manuscript and their assistance. They are also grateful to several previous students and researchers whose collaborative research is discussed here. Finally, they are grateful to NSERC of Canada, the Canada Research Chair program and the CNRS of France for supporting this research.


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Copyright information

© Springer International Publishing AG 2017

Authors and Affiliations

  1. 1.Dept. of Electrical and Computer EngineeringMcMaster UniversityHamiltonCanada
  2. 2.Institute of Electronic and SystemsUniversity of MontpellierMontpellierFrance

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