# Electrical Characterization of Semiconductor Materials and Devices

## Abstract

Semiconductor materials and devices continue to occupy a preeminent technological position due to their importance when building integrated electronic systems used in a wide range of applications from computers, cell-phones, personal digital assistants, digital cameras and electronic entertainment systems, to electronic instrumentation for medical diagnositics and environmental monitoring. Key ingredients of this technological dominance have been the rapid advances made in the quality and processing of materials – semiconductors, conductors and dielectrics – which have given metal oxide semiconductor device technology its important characteristics of negligible standby power dissipation, good input–output isolation, surface potential control and reliable operation. However, when assessing material quality and device reliability, it is important to have fast, nondestructive, accurate and easy-to-use electrical characterization techniques available, so that important parameters such as carrier doping density, type and mobility of carriers, interface quality, oxide trap density, semiconductor bulk defect density, contact and other parasitic resistances and oxide electrical integrity can be determined. This chapter describes some of the more widely employed and popular techniques that are used to determine these important parameters. The techniques presented in this chapter range in both complexity and test structure requirements from simple current–voltage measurements to more sophisticated low-frequency noise, charge pumping and deep-level transient spectroscopy techniques.

The continued evolution of semiconductor devices to smaller dimensions in order to improve performance – speed, functionality, integration density and reduced cost – requires layers or films of semiconductors, insulators and metals with increasingly high quality that are well-characterized and that can be deposited and patterned to very high precision. However, it is not always the case that improvements in the quality of materials have kept pace with the evolution of integrated circuit down-scaling. An important aspect of assessing the material quality and device reliability is the development and use of fast, nondestructive and accurate electrical characterization techniques to determine important parameters such as carrier doping density, type and mobility of carriers, interface quality, oxide trap density, semiconductor bulk defect density, contact and other parasitic resistances and oxide electrical integrity. This chapter will discuss several techniques that are used to determine these important parameters. However, it is not an extensive compilation of the electrical techniques currently used by the research and development community; rather, it presents a discussion of some of the more widely used and popular ones [20.1, 20.2, 20.3, 20.4].

An important aspect of electrical characterization is the availability of appropriate test components [20.1, 20.2, 20.3, 20.4]. In this chapter, we concentrate on discussing techniques that use standard test devices and structures. In addition, we will use the metal–oxide–semiconductor field-effect transistor (MOSFET ) whenever possible because they are widely available on test chips. This is also motivated by the fact that MOSFETs continue to dominate the semiconductor industry for a wide range of applications from memories and microprocessors to signal and imaging processing systems [20.5]. A key reason for this dominance is the excellent quality of the silicon wafers and the silicon–silicon dioxide interface, both of which play critical roles in the performance and reliability of the device. For example, if the interface has many defects or interface states, or it is rough, then the device’s carrier mobility decreases, low-frequency noise increases and its performance and reliability degrades. In particular, it is not only the interface that is important, but also the quality of the oxide; good-quality oxide prevents currents from flowing between the gate and substrate electrodes through the gate oxide. Both interface and oxide quality allows for excellent isolation between the input and output terminals of the MOSFETs, causing it to behave as an almost ideal switch. Therefore, it is important to have good experimental tools to study the interface properties and the quality of the gate dielectric.

Electrical characterization of semiconductors and the semiconductor–dielectric interface is important for a variety of reasons. For example, the defects at and in the interfacial oxide layer in silicon–silicon dioxide (Si–SiO_{2}) systems and in the bulk semiconductor play critical roles in their low-frequency noise, independent of whether the device is surface-controlled such as a MOSFET, or a bulk transport device such as a polysilicon emitter bipolar junction transistor (PE BJT ). These defects can affect the charge transfer efficiency in charge coupled devices (CCD s), p–n photodiodes or complementary metal-oxide-semiconductor (CMOS ) imagers, and can be the initiation point of catastrophic failure of oxides. Interface and bulk states can act as scattering centers to reduce the mobility in MOSFETs, thus affecting their performance parameters such as switching speed, transconductance and noise. This chapter is devoted to the electrical characterization of semiconductors, insulators and interfaces. In the first part (Sects. 20.1 and 20.2 ), the basic electrical properties of materials (such as resistivity, concentration and mobility of carriers) are studied. The main measurement techniques used to determine these electrical parameters are presented. Due to its increasing importance in modern ultrasmall geometry devices, electrical contacts are also studied. All of the characterization techniques presented in this first part are associated with specially designed test structures. In the second part (Sects. 20.4–20.7 ), we use active components such as capacitors, diodes and transistors (mainly MOSFETs) in order to determine more specific electrical parameters such as traps, oxide quality and noise level that are associated with material or devices. Of course this involves specific measurement techniques that are often more sophisticated than those discussed in the previous two sections.

## 20.1 Resistivity

Resistivity is one of the most important electrical parameters of semiconductors [20.1, 20.2, 20.3, 20.4]. First, we present the basic physical relations concerning the bulk resistivity. The main electrical measurement techniques are then described: the two oldest ones that are still relevant today – the *four-point-probe* technique and the *van der Pauw* technique – and then the *spreading resistance* technique. Second, because it is closely linked with bulk resistivity measurement techniques and it is increasingly important in modern ultrasmall geometry devices, contact resistivity will be presented. Special attention will be given to *Kelvin contact resistance* (KCR ) *measurement* and the *transmission line measurement* (TLM ) techniques.

### 20.1.1 Bulk Resistivity

#### Physical Approach, Background and Basics

*ρ*is an intrinsic electrical property related to carrier drift in materials such as metals and semiconductors [20.6]. From a macroscopic point of view, the resistivity

*ρ*can be viewed as the normalization of the bulk resistance (

*R*) by its geometrical dimensions – the cross-sectional area (

*A*=

*W*

*t*) through which the current flows, and the distance between the two ideal contacts

*L*, as shown in Fig. 20.1 . The resistivity is given by

*ρ*

_{s}is often used instead of the bulk resistivity

*ρ*. The sheet resistivity

*ρ*

_{s}is the bulk resistivity divided by the sample’s thickness

*t*. This normalized parameter is related to the resistance of a square of side

*L*. For this particular geometry in Fig. 20.1 , since

*A*=

*W*

*t*, then

*ρ*

_{s}=

*R*

_{□}, the sheet resistance. The unit of sheet resistance is Ω/square or Ω∕ □. The parameter

*R*

_{□}is convenient for integrated circuit designers because it allows them to quickly design the geometry for a specific value of resistance using very thin implanted or diffused semiconductor regions or polycrystalline layers. Resistivity (or its inverse, the conductivity

*σ*in \(\mathrm{\Upomega{}^{-1}{\,}cm^{-1}}\) or S ∕ cm) and its variation with temperature is often used to classify material into metals, semiconductors and insulators.

*E*and the drift current density

*J*; that is, \(J=\left(1/\rho\right)E\). It can be defined by the microscopic relation

*q*is the electronic charge,

*n*and

*p*are the free electron and hole concentrations, and

*μ*

_{ n }and

*μ*

_{ p }are the electron and hole drift mobilities, respectively. In this way, the resistivity is related to fundamental semiconductor parameters: the number of free carriers, and their ability to move in the lattice when an electric field is applied.

*N*

_{D}) -doped, or p-type or acceptor (

*N*

_{A}) -doped semiconductors, the free carrier densities are determined by the ionized impurities (

*N*

_{D}or

*N*

_{A}≫ the intrinsic carrier concentration

*n*

_{i}), then (20.2 ) can be simplified to

*N*

_{D}≫

*N*

_{A}or

*N*

_{A}≫

*N*

_{D}in a typical semiconductor layer.

#### Measurement Techniques

*I*flows, as shown in Fig. 20.1. Thus, the measured resistance and knowledge of the geometrical dimensions can lead to an estimate for the bulk resistivity according to (20.1). Unfortunately the measured resistance (

*R*

_{mea}) includes the unexpected contact resistance ( 2

*R*

_{c}) , which can be significant for small-geometry samples because

*R*

_{c}is strongly dependent on the metal-semiconductor structure. Therefore, special processing technologies are used to minimize the influence of

*R*

_{c}(Sect. 20.1.2). Now, the measured resistance is expressed as

*R*

_{sp}) under the two probes must also be added, as shown in Fig. 20.2. In this case, (20.5) becomes

*R*

_{sp}for a cylindrical contact of radius

*r*, and for a semi-infinite sample, it can be expressed by

*r*,

*R*

_{sp}is given by

*spreading resistance*technique measurement. Nevertheless, despite the lack of accuracy of the two contact techniques, it can be sufficient for monitoring some process steps and it is often used in the semiconductor industry as a process monitor.

##### Four-Point Probe Technique

*V*

_{2}, induced by the current flowing from probe 1 to probe 4 is given by:

*I*through probes 1 and 4, the resistivity can be determined using (20.9a) and (20.9b) as

*t*and the sample surface are very large (→ ∞ ) , and the probes’ locations must be far from any boundary. Because these relations can be applied only to large ingots, then in many cases a correction factor

*f*must be introduced in order to take into account the finite thickness and surface of the sample and its boundary effects. Further, for epitaxial layers,

*f*must also consider the nature of the substrate – whether it is a conductor or an insulator. Thus, (20.11 ) becomes

*s*is usually on the order of a millimeter, then the correction factor due to the thickness is

If the probe header is too close to any boundary, then (20.13) is no longer valid and another correction factor must be introduced. This correction factor is close to 1 until the ratio *a* ∕ *s* is greater than 2, where *a* is the distance from the edge of the sample that is shown in Fig. 20.3. A study of various 8 inch n- and p-type silicon wafers have demonstrated that the edge exclusion limit is 5 mm [20.7].

In the case of a different arrangement of probes, for instance a square array or when a different measurement configuration of the four-point collinear probes is used, such as current injection between probes 1 and 3, other specific correction factors are required. Here, rather than detail all the different correction factors, complementary information can be found in [20.4, Chap. 4] and [20.3, Chap. 1].

Taking into account the appropriate correction factors as well as some specific material parameters such as hardness or surface oxidation, it is possible to map the resistivities of different types of semiconductor wafers or deposited semiconductor layers with an accuracy better than 1*%* over a large range of resistivity values using commercial equipment and appropriate computational techniques.

##### Van der Pauw Technique

*van der Pauw*[20.8] measurement technique allows for the determination of resistivity on a sample of arbitrary shape using four small contacts placed on the periphery, as shown in Fig. 20.4. Then, the resistivity of a uniform sample of thickness

*t*is given by

*R*

_{A}and

*R*

_{B}are resistances measured by injecting current on two adjacent contacts and by measuring the voltage drop on the two remaining ones. With the notation in Fig. 20.4, one can define

*R*

_{ f }obtained from

*R*

_{A}=

*R*

_{B},

*R*

_{ f }= 1 and

*f*= 1, and (20.14) becomes

##### Spreading Resistance Technique

The spreading resistance technique is based on the modeling of current spreading from a probe tip or a small metallic contact and flowing into a bulk semiconductor, as shown previously in Fig. 20.2. Equations (20.7) and (20.8) presented above are for cylindrical probes and hemispherical probes, respectively. Basically, the principle of this method is opposite to the previous four-contact techniques where the separation of the current injection from the measured voltage drop was used to avoid the spreading resistance. Here, the spreading resistance is expected to be the dominant term in (20.6). Only two contacts are needed: two closely aligned probes, a small top contact probe or a metallic contact and a large bottom contact. In the first case, surface mapping can be performed, but the main use of this compact probe configuration is for resistivity profiling using a bevelled sample [20.3]. The second configuration has been used to measure the substrate resistivity of silicon integrated circuits where simple test structures – for example the square top contact of 25 μm × 25 μm and 50 μm × 50 μm shown in [20.12] – have been included on a test chip.

*L*

_{eff}from 295 nm without extra implantations to 229 nm with the extra implantations.

### 20.1.2 Contact Resistivity

The contact resistance of an active device and interconnection becomes larger as the dimensions are scaled down. As a consequence, the performance of single transistors as well as integrated circuits can be seriously limited by increasing *RC* time constants and power consumption. This is of major interest for the semiconductor industry, as reported by the International Technology Roadmap for Semiconductors, ITRS 2001 [20.5], and in [20.13].

#### Contact Resistance Elements

*R*

_{c}is the resistance localized from a contact pad, a probe or from the metallization process to an active region. However, it does not include all of the access resistances between these two regions, as shown in Fig. 20.8a for a horizontal contact and Fig. 20.8b for a vertical contact.

*R*

_{m}, the interfacial metal-semiconductor resistance

*R*

_{i}, and the resistance associated with the semiconductor just below the contact in the contact region

*R*

_{sc}. Thus, the contact resistance can be expressed as

*R*

_{sc}cannot be accurately defined because the boundary between the contact and access regions is very difficult to determine due to (for example) interdiffusion of metal and semiconductor atoms, and because the current flow into this region is not homogeneous due to current spreading and lateral or vertical current crowding at the periphery of the contact. The relative importance of each component of

*R*

_{c}is strongly dependent on different parameters of the process itself – annealing temperature, doping density and the geometry used (lateral or vertical).

*ρ*

_{c}, which is referred to as the specific contact resistance in Ω cm

^{2}, and

*ρ*

_{c}is given by

*A*

_{ceff}is the effective contact area; that is, the current injection area. The concept of an effective contact area can be approximated by the contact geometry in the case of a vertical contact in Fig. 20.8b. However,

*A*

_{ceff}is more difficult to specify for a lateral contact, where a transfer length

*L*

_{T}, representing the length where the current flow transfers from the contact into the semiconductor just underneath, must be introduced, as shown in Fig. 20.8a.

*L*

_{T}is defined as the length over which the voltage drops to e

^{−1}of its value at the beginning of the contact [20.3], and is given by

*ρ*

_{sc}is the sheet resistivity of the semiconductor below the contact.

*R*

_{i}in (20.18 )),

*ρ*

_{i}, can be determined from the well-known Schottky theory of metal–semiconductor contacts. The interfacial resistivity

*ρ*

_{i}is defined by

*J*–

*V*characteristic of a metal–semiconductor contact in the case of a low-doped semiconductor is given by

*A*

^{∗}is Richardson’s constant, and

*T*the absolute temperature.

*φ*

_{B}is the barrier height formed at the metal–semiconductor interface – the difference between the vacuum level and the Fermi level of the metal and of the semiconductor materials respectively, and

*φ*

_{B}is given by

*φ*

_{M}is the metal work function and

*χ*the semiconductor electron affinity.

*ρ*

_{i,TE}is

*φ*

_{B}is positive and weakly dependent on the metal–semiconductor material.

*φ*

_{B}is \(\approx 2E_{\mathrm{g}}/3\) for an n-type semiconductor and \(\approx E_{\mathrm{g}}/3\) for a p-type semiconductor. Therefore, high values of interfacial resistivity

*ρ*

_{i,TE}are usually obtained except when narrow bandgap semiconductors are used.

*ε*

_{s}is the permittivity of the semiconductor and

*m*

_{n}

^{∗}is the effective mass of the electron.

*ρ*

_{i,T}is found to be

*ρ*

_{i,TE}from (20.24) to

*ρ*

_{i,T}from (20.27), we see that a highly doped layer can significantly reduce the interfacial resistivity. For \(N_{\mathrm{D}}\geq{\mathrm{10^{19}}}\,{\mathrm{cm^{-3}}}\), the tunneling process dominates the interfacial resistivity, while for \(N_{\mathrm{D}}\leq{\mathrm{10^{17}}}\,{\mathrm{cm^{-3}}}\), the thermionic emission current is dominant.

As most semiconductors such as Si, SiGe, GaAs, InP are of relatively wide bandgap, the deposition of a heavily doped layer before the metallization is commonly used in order to form a tunneling contact. For compound semiconductor manufacturing processes, the contact layer is generally formed from the same semiconductor material, or at least from the same material as the substrate. For silicon and related materials such as SiGe alloys or polysilicon, silicidation techniques are commonly used to make the contact layer with very thin silicide layers such as CoSi_{2} or TiSi_{2} layers.

#### Measurement Techniques

As mentioned above, it is difficult to accurately model the contact resistance, so direct measurements of the contact resistance or of the contact resistivity are of great importance. The two main test structures used to determine contact characteristics will now be discussed: the *cross Kelvin resistor* (CKR ) *test structure* and the *transmission line model* (*TLM*) structure.

##### Kelvin Test Structure

*R*

_{c}is determined from the potential drop in the contact window (

*V*

_{34}) when a current

*I*is forced through the contact window from contact pad 1 to pad 2, and

*R*

_{c}is

*R*

_{c}and knowledge of the contact area

*A*allows for direct extraction of the contact resistivity

*ρ*

_{c}, given by

##### Transmission Line Model Test Structures

*L*

_{i}between the contacts. This leads to a scaled planar resistor structure. Each resistor changes only by its distance

*L*

_{i}between two adjacent contacts, as shown in Fig. 20.13, and it can be expressed by

*L*

_{i}, and according to (20.30), the layer sheet resistivity

*ρ*

_{s}and the contact resistance

*R*

_{c}can be deduced from the slope and from the intercept at

*L*

_{i}= 0 respectively, as shown in Fig. 20.14

*ρ*

_{c}) or the specific contact resistance (

*R*

_{c}

*A*

_{ceff}) , given by

*L*

_{T}. According to (20.20 ), and assuming that the sheet resistance under the contact

*ρ*

_{sc}is equal to the sheet resistance between the contacts

*ρ*

_{s}, then

*L*

_{T}can be expressed by (20.20).

*R*

_{c}into (20.32) in (20.30) leads to

*R*

_{i}= 0 allows us to determine the value of

*L*

_{T}. The main advantage of the

*TLM*method is its ability to give two main electrical parameters, the resistivity of the semiconductor contact layer

*ρ*

_{s}and the contact resistance

*R*

_{c}. However, this is done at the expense of a questionable assumption that the sheet resistance under the contact must be equal to the sheet resistance between the contacts. More on this technique can be found in [20.3].

## 20.2 Hall Effect

*n*or

*p*) or the carrier mobility (

*μ*

_{ n }or

*μ*

_{ p }) to be fundamental or microscopic parameters. For a semiconductor material, the resistivity is related to these two parameters (density and mobility) by (20.2 ). The strength of the Hall effect is to directly determine the sheet carrier density by measuring the voltage generated transversely to the current flow direction in a semiconductor sample when a magnetic field is applied perpendicularly, as shown in Fig. 20.15 a. Together with a resistivity measurement technique such as the four-point probe or the van der Pauw technique, Hall measurements can be used to determine the mobility of a semiconductor sample.

In modern semiconductor components and circuits, knowledge of these two fundamental parameters *n* ∕ *p* and *μ*_{ n } ∕ *μ*_{ p } is critical. Currently, Hall effect measurements are one of the most commonly used characterization tools in the semiconductor industry and research laboratories. This is not just because of the parameters that can be extracted for use in device modeling or materials characterization, but also because of the quantum Hall effect (QHE ) in condensed matter physics [20.18]. Moreover, in the applied electronics domain, one should note the development of different sensors based on the physical principle of the Hall effect, such as commercial CMOS Hall sensors.

As is very often the case, the development of a characterization technique is related to its cost, simplicity of implementation and ease of use. Since these practical characteristics are satisfied even when specially shaped samples are required, then the Hall effect measurement technique has become a very popular method of characterizing materials.

In this section, we will first present the physical principle of the Hall effect. Then we will show how it can be used to determine the carrier density and mobility. Finally, the influence of the Hall scattering factor will be presented, followed by some practical issues about the implementation of the Hall effect method.

### 20.2.1 Physical Principles

The Hall effect was discovered by *Hall* in 1879 [20.19] during an experiment on current transport in a thin metal strip. A small voltage was generated transversely when a magnetic field was applied perpendicularly to the conductor.

The basic principle of this Hall phenomenon is the deviation of some carriers from the current line due to the Lorentz force induced by the presence of a transverse magnetic field. As a consequence, a voltage drop *V*_{H} is induced transversely to the current flow. This is shown in Fig. 20.15a for a p-type bar-shaped semiconductor, where a constant current flow *I*_{ x } in the *x*-direction and a magnetic field in the *z*-direction results in a Lorentz force on the holes. If both holes and electrons are present, they deviate towards the same direction. Thus, the directions of electrical and magnetic fields must be accurately specified.

*v*

_{ x }is the carrier velocity in the

*x*-direction. Assuming a homogeneous p-type semiconductor

*y*-direction

*E*

_{ y }. When the magnetic force

*F*

_{L}is balanced by the electric force

*F*

_{EL}, then the Hall voltage

*V*

_{H}is established, and from a balance between

*F*

_{L}and

*F*

_{EL}, we get

*V*

_{H}is given by

*B*and the current

*I*are known, then the measurement of the Hall voltage gives the hole sheet concentration

*p*

_{s}from

*t*is known, then the bulk hole concentration can be determined (see (20.41 )) and expressed as a function of the Hall coefficient

*R*

_{H}, defined as

*ρ*is known or can be measured at the same time using a known sample such as a Hall bar or van der Pauw structure geometry in zero magnetic field, then the carrier drift mobility can be obtained from

Whatever the geometry used for Hall measurements, one of the most important issues is related to the offset voltage induced by the nonsymmetric positions of the contact. This problem, and also those due to spurious voltages, can be controlled by two sets of measurements, one for a magnetic field in on direction and another for a magnetic field in the opposite direction.

The Hall effect has also been investigated on specific structures, and an interesting example can be found in reference [20.21], where a Hall bar structure was combined with a double-gate n-silicon-on-insulator (SOI ) MOSFET. This was done in order to understand the mobility behavior in ultra-thin devices and to validate the classical drift mobility extraction method based on current–voltage measurements.

In the Hall effect experiment, the measurement of the Hall coefficient *R*_{H} leads to the direct determination of the carrier concentration and mobility. Moreover, the sign of *R*_{H} can be used to determine the type of conductivity of the semiconductor sample. If various types of carriers are present, then the expression for *R*_{H} becomes more complex and approximations in the limit of low and high magnetic field are necessary [20.3, Chap. 8].

We have so far discussed the Hall effect on a uniformly doped substrate or single semiconductor layer deposited on an insulating or semi-insulating substrate. In the case of a semiconductor layer deposited on a semiconducting substrate of opposite doping type, Hall effect measurements can be performed if the space charge region can act as an insulator. In the case of multilayers, the problem is more difficult, but an approximation for transport experiments has been developed for two-layer structures [20.22] and applied to different metal–semiconductor field-effect-transistor (MESFET ) structures, for instance [20.23].

### 20.2.2 Hall Scattering Factor

*r*

_{H}must be taken into account. In this case (20.41), (20.43) and (20.44 ) must be modified as follows

*τ*(

*E*) , and

*r*

_{H}is given by

*r*

_{H}at low magnetic fields can be determined by measuring the Hall coefficient in the limit of both high and low magnetic fields [20.25] using

*r*

_{H}is found to vary between 0.6 and 2 [20.26]. However, due to valence band distortion effects, values as low as 0.26 have been found in strained p-type SiGe epilayers [20.27]. Therefore, the Hall carrier concentration and especially the Hall mobility must be distinguished from carrier concentration and carrier drift mobility.

*T*) dependences, then the Hall mobility as function of temperature is often used to separate the different scattering processes. An example is given in Fig. 20.16 for silicon-on-insulator (SOI) films [20.24]. The increase in the mobility between 4 and 45 K, which is given by

*μ*∝

*T*

^{2.95}, is related to the ionized donor scattering mechanism. The decrease in mobility between 46 and 120 K given by \(\mu\propto T^{-1.55}\) is associated with lattice scattering. However, after 150 K, the rapid decrease in mobility observed, where \(\mu\propto T^{-2.37}\), suggests that other scattering mechanisms as well as the lattice scattering mechanism, such as electron or phonon scattering, must be taken into account.

## 20.3 Capacitance–Voltage Measurements

*C*–

*V*) measurements are normally made on metal-oxide semiconductor (MOS ) or metal-semiconductor (MS ) structures in order to determine important physical and defect information about the insulator and semiconductor materials. For example, high-frequency (HF) and low-frequency (LF ) or quasi-static

*C*–

*V*measurements in these structures are used to determine process and material parameters – insulator thickness, doping concentration and profile, density of interface states, oxide charge density, and work function or barrier height. In this section, we describe various

*C*–

*V*measurements and how they can be used to provide process parameters as well as valuable information about the quality of the materials. A typical

*C*–

*V*curve for a MOS capacitor with an n-type semiconductor is shown in Fig. 20.17. For a MOS capacitor with a p-type substrate, the

*C*–

*V*curve be similar to that in Fig. 20.17, but reflected about the

*y*-axis.

### 20.3.1 Average Doping Density by Maximum–Minimum High-Frequency Capacitance Method

*C*

_{OX}) and strong inversion \((C_{\text{HF},\min})\) to determine the average doping density [20.29, pp. 406–408]. Note that under strong inversion and at high frequencies, the interface trap capacitance is negligible (

*C*

_{it}≈ 0 ) . Under strong inversion, the depletion width (

*w*

_{max}) is a maximum and so the high frequency capacitance per unit area \(C_{\text{HF},\min}\) is a minimum, since the minority carriers cannot respond to the high-frequency signal. Since the inversion layer is very thin compared to the depletion layer, then

*ε*

_{Si}is the permittivity of silicon and

*C*

_{OX}is the gate oxide capacitance per unit area.

*w*

_{max}, the band bending

*ψ*

_{max}is a maximum, and it is

*n*, and

*n*

_{ i }is the thermally generated carrier concentration in silicon. For a uniformly doped sample,

*n*and the measured capacitance can be established [20.29, p. 407] as

*n*that can be solved numerically by iteration. Figure 20.18 shows the solutions as function of

*C*

_{HF,min}∕

*C*

_{OX}with oxide thickness, and this can be used to obtain the average doping

*n*graphically. Equation (20.53) can be further simplified by neglecting the term \(0.5\ln[2\ln(n/n_{i})-1]\), and assuming

*C*

_{OX}=

*C*

_{HF,max}[20.30]. Also, an approximation of (20.53) for the average doping concentration

*n*in unit cm

^{−3}is obtained in [20.4] and [20.31] for silicon MOS structures at room temperature, and this is given by

^{2}of area)

*C*

_{DM}is defined as

^{2}.

### 20.3.2 Doping Profile by High-Frequency and High–Low Frequency Capacitance Methods

*C*

_{D}and the oxide capacitance per unit area

*C*

_{OX}are connected in series; that is, that the measured high frequency capacitance

*C*

_{HF}is given by

*V*

_{G}of the MOS structure, the depletion thickness

*w*(

*V*

_{G}) is obtained from

*C*

_{D}as

*n*(

*V*

_{G}) is given by the slope of the ( 1 ∕

*C*

_{HF})

^{2}versus

*V*

_{G}characteristic, given by

*C*

_{HF}

^{2}versus

*V*

_{G}(Fig. 20.19) can yield important information about the doping profile. The average

*n*is related to the reciprocal of the slope in the linear part of the 1 ∕

*C*

_{HF}

^{2}versus

*V*

_{G}curve, and the intercept with

*V*

_{G}at a value of 1 ∕

*C*

_{OX}

^{2}is equal to the flat-band voltage

*V*

_{FB}caused by the fixed surface charge

*Q*

_{SS}and the gate–semiconductor work function

*ψ*

_{MS}[20.3, 20.30].

Equation (20.58) does not take into account the impact of interface traps, which cause the *C*–*V* curve to stretch. The traps are slow and do not respond to the high frequency of the test signal, but they do follow the changes in the gate bias. Therefore, ∂ *V*_{G} must be replaced with ∂ *V*_{G0} in (20.58), with ∂ *V*_{G0} representing the case when no interface traps are present.

*V*

_{G0}can be obtained by comparing high- and low-frequency (quasi-static)

*C*–

*V*curves for a MOS structure at the same gate biases

*V*

_{G}. Therefore, the ratio \(\partial V_{\mathrm{G0}}/\partial V_{\mathrm{G}}\) can be found at any gate bias

*V*

_{G}, since the band-bending is the same for both HF and LF capacitances. In [20.29, Sect. 9.4], it is shown that

*C*–

*V*curves due to the interface states induced by stress in Fig. 20.20a-ca causes a disparity in the doping profile in Fig. 20.20a-cb if only the high frequency capacitance is used. The disparity is well-suppressed in Fig. 20.20a-cc by the high–low frequency capacitance measurement, taking into account the stretching of the

*C*–

*V*characteristics. Provided that the depletion layer capacitance is measured at a high frequency, the depletion layer width

*w*is still obtained by (20.57).

*w*

_{max}(20.52) and the resolution

*Δ*

_{ w }of the doping profile by means of

*C*–

*V*measurements is limited by the maximum band-bending

*ψ*

_{max}and the extrinsic Debye length

*λ*

_{Debye}, given by (20.51) and (20.61 ), respectively, and

*λ*

_{Debye}is

*w*of between 3

*λ*

_{Debye}and \(w_{\max}/2\), when the MOS structure is in depletion and weak inversion, but not in accumulation. That is,

*C*

_{LF}< 0.7

*C*

_{OX}as a simple rule. As illustrated in Fig. 20.21 , the range of

*w*values between 3

*λ*

_{Debye}and equilibrium, obtained via quasi-static

*C*–

*V*measurements, cover about half-a-decade. With proper corrections, the lower distance decreases to one Debye length [20.30]. Using nonequilibrium (transient)

*C*–

*V*measurements in deep depletion, the profiling can be extended to higher distances by about an order of magnitude, but further limitations can appear due to the high-frequency response of the interface charge, measurement errors, avalanche breakdown in deep depletion, or charge tunneling in highly doped substrates and thin oxides. More details are presented in [20.29].

### 20.3.3 Density of Interface States

*C*–

*V*curves occurs, as illustrated in Fig. 20.20a-c . A quantitative treatment of this

*stretch-out*can be obtained from Gauss’ law as

*Q*

_{S}and

*Q*

_{IT}are the surface and interface trap charges (per unit area), which are both dependent on the surface band-bending

*ψ*

_{S}, \(Q_{\mathrm{T}}=Q_{\mathrm{S}}+Q_{\mathrm{IT}}\) is the total charge in the MOS structure,

*C*

_{OX}is the gate capacitance (per unit area), and

*V*

_{G}is the bias applied at the gate of the MOS structure. For simplicity, the (gate metal)-to-(semiconductor bulk) potential

*ψ*

_{MS}is omitted in (20.62), but in a real structure the constant

*ψ*

_{MS}must be subtracted from

*V*

_{G}. As follows from (20.62), small changes ∂

*V*

_{G}in gate bias cause changes ∂

*ψ*

_{S}in the surface potential bending, and the surface

*C*

_{S}and interface trap

*C*

_{IT}capacitances (both per unit area) can represent

*Q*

_{S}and

*Q*

_{IT}, given by

*C*

_{S}and

*C*

_{IT}are in parallel and in series with the

*C*

_{OX}, respectively. Therefore, the measured low-frequency capacitance

*C*

_{LF}(per unit area) of the MOS structure becomes

*C*–

*V*curve can arise due to a non-zero value of

*C*

_{IT}, which deviates from the ideal case of

*C*

_{IT}= 0.

*D*

_{IT}is the density of interface states per unit area ( cm

^{2}) and per unit energy (1 eV) in units of \(\mathrm{cm^{-2}{\,}e{\mskip-2.0mu}V^{-1}}\). Since the occupancy of the interface states has a Fermi–Dirac distribution, then upon integrating over the silicon band-gap, the relation between

*C*

_{IT}and

*D*

_{IT}is

*n*, and

*n*

_{ i }is the thermally generated carrier concentration in silicon. Since the derivative of the Fermi–Dirac distribution is a sharply peaking function, then

*C*

_{IT}(

*ψ*

_{S}) at particular

*ψ*

_{S}probes

*D*

_{IT}(

*φ*

_{B}+

*ψ*

_{S}) over a narrow energy range of

*k*

_{B}

*T*∕

*q*, in which

*D*

_{IT}can be assumed to be constant and zero outside this interval. Thus, varying the gate bias

*V*

_{G}, and therefore

*ψ*

_{S}, (20.65) can be used to obtain the density of states

*D*

_{IT}at a particular energy shift

*q*(

*φ*

_{B}+

*ψ*

_{S}) from the silicon intrinsic (mid-gap) energy

*E*

_{i}.

It is evident from (20.64) and (20.65) that the experimental values for *D*_{IT} can be obtained only when *C*_{IT}, and *ψ*_{S} are determined from *C*–*V* measurements. The simplest way to determine *φ*_{B} is to get the average doping density *n* using the maximum–minimum high-frequency capacitance method (see (20.53) and Fig. 20.18), or to use the values of *n* from doping profiles at 0.9 *w*_{max} – see (20.59) [20.30]. Either the high-frequency or the low-frequency *C* − *V* measurement can be used to obtain *C*_{IT}, but it is necessary to calculate *C*_{S} as function of *ψ*_{S}, which makes it difficult to process the experimental data.

*D*

_{IT}is the combined high–low frequency capacitance method [20.29, Sect. 8.2.4, p. 332]. The interface traps respond to the measurement of low–frequency capacitance

*C*

_{LF}, whereas they do not respond to the measurement of the high-frequency measurement

*C*

_{HF}. Therefore,

*C*

_{IT}can be obtained from measurements by

*subtracting*

*C*

_{HF}from

*C*

_{LF}, given by

*D*

_{IT}from

*C*–

*V*measurements (see also [20.3, p. 371]) as

*C*

_{IT}and

*D*

_{IT}as function of gate bias

*V*

_{G}. However, if

*D*

_{IT}needs to be plotted as a function of the position in the energy band-gap, the surface band-bending

*ψ*

_{S}must also be determined as function of gate bias

*V*

_{G}, as follows from (20.65).

*ψ*

_{S}and

*V*

_{G}. One way is to create a theoretical plot of

*C*

_{HF}versus

*ψ*

_{S}and then, for any choice of

*C*

_{HF}, a pair of values for

*ψ*

_{S}and

*V*

_{G}is found [20.29, p. 327]. This method is relatively simple if the doping concentration

*n*in the silicon is uniform and known, because the high-frequency silicon surface capacitance

*C*

_{S}under depletion and accumulation is a simple function of the band-bending

*ψ*

_{S}, and the flat-band capacitance

*C*

_{FB}[20.29, pp. 84, 97, 164] is given by

*C*

_{S}is in series with

*C*

_{OX}, then the theoretical

*C*

_{HF}is obtained as a function of the band-bending

*ψ*

_{S}by

_{2}as the insulator, the ratio

*C*

_{HF}(

*V*

_{FB}) ∕

*C*

_{OX}at gate bias for flat-band conditions is given [20.3, p. 349] by

*t*

_{ox}is the oxide thickness ( cm ) ,

*n*is the doping ( cm

^{−3}) , and the

*T*is the temperature ( K ) .

It was demonstrated in [20.29] that the method of using a theoretical plot to obtain the relation between *ψ*_{S} and *V*_{G} works well in the case of uniformly doped silicon even if only high-frequency *C*–*V* measurements are used to obtain the density of states; that is, the 1 ∕ *C* _{HF} ^{2} versus *V*_{G} plot is almost a straight line. However, with substrates that are not uniformly doped, the method is inconvenient because the corrections in (20.68) and (20.69) are difficult to implement. Therefore, in practice, a method based on low-frequency *C*–*V* measurement is preferred [20.30].

*C*–

*V*measurement was first used to obtain the relation between

*ψ*

_{S}and

*V*

_{G}[20.34]. This method is based on the integration of (20.66) from an initial gate bias

*V*

_{G0}, arbitrarily chosen either under strong accumulation or strong inversion, to the desired

*V*

_{G}at which the band-bending

*ψ*

_{S}(

*V*

_{G}) is to be obtained. Since

*C*

_{IT}is part of (20.66), then the low-frequency

*C*–

*V*curve [20.29, p. 93] is integrated as

*ψ*

_{S0}is selected such that

*ψ*

_{S}(

*V*

_{FB}) = 0 when integrating from

*V*

_{G0}to the flat-band gate voltage

*V*

_{FB}. In this case,

*V*

_{FB}is usually obtained beforehand from the point of

*V*-intercept with 1 ∕

*C*

_{OX}

^{2}when extrapolating the linear part of the 1 ∕

*C*

_{HF}

^{2}versus

*V*

_{G}curve toward the

*V*

_{G}axis (Fig. 20.19). After determining

*ψ*

_{S0}, (20.72) provides the relation between

*ψ*

_{S}and

*V*

_{G}. Thus, the density of states

*D*

_{IT}obtained from (20.67) as function of

*V*

_{G}using the combined high–low frequency capacitance method can be plotted against the position of

*D*

_{IT}in the silicon band gap, as given by (20.65). High and low frequency

*C*–

*V*measurements can therefore be used to plot the data, as illustrated in the insert of Fig. 20.22.

*D*

_{IT}(Fig. 20.23 ). For some of these techniques, the ability to sense the energy position of

*D*

_{IT}in the band-gap of silicon is summarized in [20.3]. Most of them use

*C*–

*V*measurements, but others are based on

*I*–

*V*measurements taken during the subthreshold operation of MOS transistors, deep-level transient spectroscopy (DLTS ), charge pumping (CP ) in a three-terminal MOS structure, cryogenic temperature measurements, and so on. Each technique has its strengths and weaknesses, which are discussed in [20.3, 20.35].

In the methods discussed above, it has been assumed that the gate bias *V*_{G} varies slowly with time, 20–50 mV ∕ s, and that the MOS structure is in equilibrium; that is, the minority carriers are generated and the inversion layer is readily formed in the MOS structure when *V*_{G} is above the threshold. However, the time constant for minority carrier generation is high in silicon (≈ 0.1 s or more), and it is possible to use nonequilibrium high-frequency *C*–*V* measurements to further analyze the properties of the MOS structure. Some applications of these methods are presented later.

## 20.4 Current–Voltage Measurements

### 20.4.1 *I*–*V* Measurements on a Simple Diode

*I*–

*V*characteristics of a p-n diode structure, the source–substrate or drain–substrate junctions can provide useful information on the quality of the junction, such as whether defects are present (they give rise to generation–recombination currents or large parasitic resistances for the contacts at the source, drain or substrate terminals). This is easily seen from the current–voltage relation given by the sum of the diffusion (

*I*

_{DIFF}) and recombination (

*I*

_{GR}) currents

*I*

_{D0}and

*I*

_{GRO}are the zero-bias diffusion and recombination currents respectively,

*n*is an ideality factor (typically 1), and

*V*

_{D}is the voltage across the intrinsic diode, which is given by

*I*

_{D}) versus

*V*

_{D}allows us to separate out the diffusion and the recombination current components. From (20.73) and (20.74), we can also use the diode’s

*I*–

*V*characteristics to determine the parasitic resistance in series with the intrinsic diode, as described in detail in [20.36]. In most cases, this

*R*

_{parasitic}is dominated by the contact resistance.

### 20.4.2 *I*–*V* Measurements on a Simple MOSFET

Simple current–voltage measurements – drain current versus gate voltage ( *I*_{DS}–*V*_{GS} ) , and *I*_{DS} versus drain voltage (*V*_{DS} ) – are routinely taken on MOSFETs in order to study their electrical characteristics; however, these can also be used to obtain useful information on the quality of the semiconductor, contacts, oxide and semiconductor–oxide interface. For example, the *I*_{DS} − *V*_{GS} characteristics at very small *V*_{DS} biases (linear region of operation) for a set of test transistors of fixed channel width and different channel lengths is often used to extract parameters such as the threshold voltage ( *V*_{T} ) , the transconductance ( *g*_{m} ) , the intrinsic mobility ( *μ*_{o} ) and the mobility degradation coefficients *θ*_{0} and *η*, the parasitic source ( *R*_{S} ) and the drain resistances ( *R*_{D} ) in series with the intrinsic channel, the channel length reduction Δ*L*, the output conductance ( *g*_{DS} ) and the subthreshold slope (*S*) [20.37].

These parameters are required for modeling and they directly impact the device’s performance. However, some of these parameters can also be used to assess the quality of the silicon–silicon dioxide (Si–SiO_{2}) interface [20.38, 20.40]. For example, interface states at the Si–SiO_{2} interface can change the threshold voltage, the subthreshold slope and the mobility, all of which will impact on the drain–source ( *I*_{DS} ) current flowing through the device. Here, we look at one parameter in more detail – the subthreshold slope *S* in mV (of *V*_{GS})/decade (of *I*_{DS}).

*D*

_{IT}) can be determined from a semi-log plot of

*I*

_{DS}−

*V*

_{GS}characteristics at very low drain biases, as shown in Fig. 20.24 . We start with the expression for the subthreshold slope

*D*

_{IT}can then be calculated from

*C*

_{IT}is determined from (20.75). In fact, a recent comparison in [20.41] of the interface trap densities extracted from capacitance, subthreshold and charge pumping measurements produced similar results, demonstrating that simple and fast

*I*–

*V*measurements based on the subthreshold technique can provide useful information on the Si–SiO

_{2}quality.

### 20.4.3 Floating Gate Measurements

The floating gate technique is another simple *I*–*V* measurement in which the evolution of the drain current *I*_{DS} is monitored after the gate bias has been removed. It has been shown to be particularly useful when monitoring early-mode hot-carrier activity in MOS transistors [20.39, 20.41]. In this measurement, we first check the oxide quality by biasing the transistor in the strong linear region (very low *V*_{DS} and a *V*_{GS} well above *V*_{T}), and then lift the gate voltage probe so that *V*_{GS} = 0 V and measure the evolution of *I*_{DS} with time. For a high-quality gate and spacer oxide, *I*_{DS} remains constant for a long time, indicating that there is negligible carrier injection across the gate oxide through Fowler–Nordheim tunneling or other leakage mechanisms.

*V*

_{GS}≈

*V*

_{DS}was chosen for a high-impact ionization-induced gate current, but a lower-than-maximum electron injection situation was used for the initial biasing condition.

*I*

_{DS}and the

*I*

_{DS}−

*V*

_{GS}characteristics of a virgin (not intentionally stressed) transistor at the same

*V*

_{DS}as the floating gate measurements, and from measurements of the total capacitance associated with the gate (

*C*

_{G}) , the gate current (

*I*

_{G}) evolution after each floating gate cycle can be determined using

*I*

_{G}−

*V*

_{GS}evolution is shown in Fig. 20.26 b. An ancillary benefit of the floating gate technique is that very small gate currents (in the fA range or even smaller) can be easily determined by measuring much larger drain currents using, for example, a semiconductor parameter analyzer. The reason for this is that the gate current is not directly measured in this technique – it is determined from

*I*

_{DS}−

*V*

_{GS}and (20.78). Also, the change in the floating gate current after the first few cycles can be used to monitor for early mode failure after statistical evaluation.

## 20.5 Charge Pumping

Charge pumping (CP) is another electrical technique that is well suited to studying semiconductor–insulator interfaces in MOSFETs [20.42, 20.43, 20.44, 20.45, 20.46, 20.47]. There are several versions of the CP technique: spatial profiling CP [20.43, 20.44, 20.45, 20.46, 20.47], energy profiling CP [20.48], and, more recently, new CP techniques [20.49] that permit the determination of both interface states ( *N*_{IT} ) and oxide traps ( *N*_{OT} ) away from the interface and inside the oxide. The charge pumping technique is more complicated than either of the *I*–*V* or floating gate methods. However, it is a very powerful technique for assessing interface quality and it works well even with very small transistor geometries and very thin gate oxides, where tunneling can be a problem.

_{2}interface . Since then, there have been numerous publications with enhancements, refinements and applications of the technique to a variety of semiconductor–insulator interfacial studies. In the basic charge pumping experiment, the gate of an NMOST (for example) is pulsed from a low value (

*V*

_{L}) when the device is in accumulation to a high value (

*V*

_{H}) when the device is in inversion. This results in the filling of traps between

*E*

_{F,ACC}(corresponding to

*V*

_{L}) and

*E*

_{F,INV}(corresponding to

*V*

_{H}) with holes and electrons, respectively. When pulsing the gate between accumulation at

*V*

_{L}and inversion at

*V*

_{H}, a current flows due to the repetitive recombination at the interface traps of minority carriers from the source and drain junctions with majority carriers from the substrate. This current is termed the charge pumping current, and it was found to be proportional to the frequency of the gate pulse, the gate area and the interface state density. Its sensitivity is better than \({\mathrm{10^{9}}}\,{\mathrm{cm^{-2}{\,}e{\mskip-2.0mu}V^{-1}}}\). In the traditional CP experiment shown in Fig. 20.27, but with \(\Updelta V_{\mathrm{S}}=|V_{\mathrm{D}}-V_{\mathrm{S}}|={\mathrm{0}}\,{\mathrm{V}}\), the gate G is connected to a pulse generator, a reverse bias

*V*

_{R}or no bias is applied to both sources S and drain D terminals, and the charge pumping current flowing in the substrate terminal,

*I*

_{CP}, is measured. To generate a typical charge pumping curve (as shown in the top part of Fig. 20.28), the base level of the pulse is varied, taking the transistor from below flat-band to above surface inversion conditions, as shown in the bottom part of Fig. 20.28.

*I*

_{CP}is given by

*N*

_{IT}(

*x*

_{d}) ) is given by

*V*

_{S}between

*V*

_{D}and

*V*

_{S}that is too small results in a difference in

*I*

_{CP}that is too small as well, and hence a large error in

*N*

_{IT}(

*x*) , as indicated from (20.83). On the other hand, values of Δ

*V*

_{S}that are too large result in a

*I*

_{D}that is too high and hence more substrate current

*I*

_{B}. This current

*I*

_{B}can interfere with

*I*

_{CP}if Δ

*V*

_{S}is large or if

*L*is very short, resulting in a large error in

*N*

_{IT}(

*x*) . The range 50–100 mV for Δ

*V*

_{S}seems to be a good compromise for the devices investigated in [20.43, 20.44]. Experimental results for spatial profiling CP measurements indicate that

*N*

_{IT}(

*x*) peaks near S∕D edges. However, after normal mode stress,

*N*

_{IT}(

*x*) only increases near D. This is shown in Fig. 20.29. More details about charge pumping can be found in a recent review [20.51].

## 20.6 Low-Frequency Noise

### 20.6.1 Introduction

Low-frequency noise (LFN ) spectroscopy requires very good experimental skills in the use of low-noise instrumentation as well as grounding and shielding techniques. Other special considerations are also required, which are discussed later. Although it is time-consuming to perform, it has been widely used to probe microscopic electrical transport in semiconductors and metals. LFN is very sensitive to defects in materials and devices, and large differences in LFN characteristics can be observed in devices with identical electrical current–voltage characteristics. This is mainly because electrical *I*–*V* measurements only probe the average or macroscopic transport in devices and so are not as sensitive to defects as LFN. Due to its sensitivity to defects, traps or generation–recombination centers, LFN has been proposed as a good tool for predicting device reliability. For example, LFN has been used to predict the reliabilities of metal films [20.52], and has been used in processing steps that produce photodetectors with better performance [20.53, 20.54]. LFN noise is sensitive to both bulk and surface defects or contaminants of a material.

Using low-frequency noise spectroscopy and biasing the transistor in saturation, we can spatially profile the defect density near the drain and source terminals for devices in normal and reverse modes of operation [20.55]. Low-frequency noise in the linear region also allows us to extract the average defect density over the entire channel region at the silicon–silicon dioxide interface [20.56, 20.57]. Noise experiments were performed on small-geometry polysilicon emitter bipolar transistors to investigate the number of interface states in the thin interfacial oxide layer between the monocrystalline and polycrystalline silicon [20.58, 20.59, 20.60, 20.61, 20.62, 20.63, 20.64, 20.65, 20.66, 20.67, 20.68]. Recent experiments using body or substrate bias ( *V*_{B} ) in a MOS transistor allowed us to look at the contribution of bulk defects (defects away from the silicon–silicon dioxide interface) and their contribution to device noise [20.69, 20.70, 20.71]. This is important since substrate biasing has been proposed as a means to cleverly manage power dissipation and speed in emerging circuits and systems [20.72].

As mentioned before, special attention must be paid to grounding and shielding in LFN measurements, as this is crucial to minimizing the effects of experimental and environmental noise sources on the device under test (DUT ). Because electric power supplies are noisy, especially at 60 Hz (in North America) and its harmonics, and this noise can dominate the noise of the DUT, batteries are often used to supply the voltage. Metal film resistors are the preferred means of changing the biasing conditions, because of their better low-noise characteristics compared to carbon resistors, for example.

With these experimental precautions taken, the noise signal from the transistor might still be too low to be directly measured using a spectrum or signal analyzer. Therefore, a low-noise voltage or current amplifier, whose input noise sources are lower than that of the noise signal, is used to boost the noise signal. In addition, other instruments might be used to measure currents or voltages, or to display the waveforms (as shown in Fig. 20.30 ). An example of a low-frequency noise characterization system that we have used to study the noise in thin film polymer transistors is shown in Fig. 20.30. Note that LFN measurements are time intensive because a large number of averages are required for smooth spectra. Also, in noise measurements, the power spectrum densities *S*_{ V } and *S*_{ I } for the noise voltages and currents are measured, in units V^{2} ∕ Hz and A^{2} ∕ Hz, respectively.

### 20.6.2 Noise from the Interfacial Oxide Layer

*f*noise, generation–recombination (g–r) noise and shot noise sources. In the case of the base current, the noise spectra can be modeled as

*f*noise when added. This is schematically shown in Fig. 20.31.

*bumps*associated with resolvable g–r noise components. This is schematically shown in Fig. 20.32.

^{2}) in Fig. 20.34 . Here, one can see how 1 ∕

*f*noise is made up of g–r spectra as the emitter geometries are scaled to smaller and smaller values. For the PE BJT with an emitter area of 0.16 μm

^{2}, a lower bound of ≈ 10

^{9}cm

^{2}can be approximated for the oxide trap density. Similar results have been obtained for MOSFETs [20.73].

### 20.6.3 Impedance Considerations During Noise Measurement

In principle, both configurations can be used for LFN measurement, but the impact of the nonideality of the amplifier (such as the input impedance, noise voltage and current) changes when the device impedance changes. Also, the noise from the bias source varies with each measurement set-up.

*S*

_{Vn}) and noise current (

*S*

_{In}) sources. The noise voltage from the bias is represented by

*S*

_{V0}. The impedance of the bias source is

*R*

_{0}, whereas the input impedance of the amplifier is neglected, since it is usually very high compared to

*R*

_{0}. The impedance of DUT is

*r*

_{d}. The noise current

*S*

_{Id}of the device that can be measured, assuming that the noise voltage at the input of the amplifier

*S*

_{Vm}=

*S*

_{Id}

*r*

_{d}

^{2}. However, the amplifier sees a different level of

*S*

_{Vm}, given by

*A*is the voltage gain of the amplifier. Therefore, the estimated value for

*S*

_{Id}is

*S*≤

*S*denotes the uncertainty in each noise source. As seen from (20.88 ), the impact of the bias source noise Δ

*S*

_{V0}and the input current noise Δ

*S*

_{In}can be reduced if the impedance of the measurement circuit

*Z*is low and the ratio

*r*

_{d}∕

*R*

_{0}is kept much less than 1; in other words, the

*voltage noise measurement is more appropriate for low-impedance devices, such as diodes at forward biasing*, and the noise floor of the measurement is limited by the input-referred voltage noise \(S_{V_{\mathrm{n}}}\) of the amplifier.

*S*

_{Im},

*Z*, the device noise

*S*

_{Id}, and the uncertainty, respectively, are given by (20.89–20.92) below

*S*

_{V0}and the input voltage noise Δ

*S*

_{In}can be reduced if the impedance of the measurement circuit

*Z*and (

*r*

_{d}+

*R*

_{0}) are both high; in other words, the

*current noise measurement is more appropriate for high-impedance devices, such as diodes at reverse biasing*, and the noise floor of the measurement is limited by the input-referred current noise \(S_{I_{\mathrm{n}}}\) of the amplifier.

This analysis above demonstrates that the choice of the measurement configuration follows our expectation that voltage should be measured in low-impedance devices and current in high-impedance devices. Also, the noise floor limiting parameter of the preamplifier is of the same type as the type of measurement; that is, input-referred noise voltage for voltage noise measurement and input-referred noise current for current noise measurement. Note that there is a trade-off between the voltage and current noise in amplifiers, which implies that the measurement configuration – either voltage or current measurement – should also be carefully selected with respect to the impedance of the device under test. In addition, four-point connection can be used to measure the noise in very low impedance devices ( *r*_{d} < 100 ) . These and other considerations for low-frequency noise instrumentation are discussed in many papers, for example [20.74, 20.75, 20.76].

## 20.7 Deep-Level Transient Spectroscopy

Deep-level transient spectroscopy (DLTS) is a fairly complicated electrical characterization technique where the temperature is varied in large range from cryogenic temperatures ( < 80 K ) to well above room temperature ( > 400 K ) . However, it is a powerful and versatile technique for investigating deep-level defects and it also gives accurate values for the capture cross-sections of defects. There are several DLTS techniques and [20.77, 20.78] provide recent reviews of the subject. In DLTS, the semiconductor device or junction is pulsed with an appropriate signal, and the resulting transient (such as capacitance, voltage or current) is monitored at different temperatures. Using these recorded transients at different temperatures, it is possible to generate a spectrum with peaks, each of which is associated with a deep level. The heights of the peaks are proportional to the defect density.

Here, we will focus on a new version of DLTS: the constant resistance (CR) DLTS technique [20.79, 20.80, 20.81]. We were able to accurately investigate bulk defects in a variety of test structures with CR-DLTS. Using body bias in a MOS transistor, we were able to distinguish interfacial and bulk defects that are important for different applications. For example, interfacial defects are important for electronic applications, and bulk defects are important for imaging or radiation detection applications. Examples of results from DLTS studies with and without body bias will be discussed.

CR-DLTS is well-suited to investigations of electrically active point defects that are responsible for the creation of deep levels in the semiconductor band-gap. CR-DLTS can also be used to distinguish bulk traps and interface traps in MOSFETs.

*t*

_{1}to

*t*

_{2}, and then plotting [

*C*(

*t*

_{1}) −

*C*(

*t*

_{2}) ] as a function of temperature, a DLTS spectrum with a characteristic peak is obtained as shown in the bottom of Fig. 20.38.

*τ*and the temperatures at which the peaks occur, Arrhenius plots are constructed in order to determine the defect energy level and its capture cross-section. Examples of DLTS spectra and Arrhenius plots associateed with CR-DLTS are presented later (in Fig. 20.40).

A block representation of the CR-DLTS system is shown in Fig. 20.39 . More details can be found in [20.79, 20.80, 20.81, 20.82, 20.83]. A discussion of the signal processing and averaging techniques used with this DLTS technique can be found in [20.82]. Here, the gate bias voltage of the field-effect transistor is adjusted using a feedback circuit so that the resistance corresponding to the source–drain conductance matches that of a reference resistor *R*_{ref}, which is typically around 1 MΩ. The voltage transient due to the change in occupancy of the traps appears as a compensation voltage on the gate. This voltage change can be regarded as a threshold voltage change because the flat-band voltage of the device changes when the occupancy of the traps change. More details on how this change in the threshold is related to the traps can be found in [20.77, 20.79, 20.81].

Some important advantages of the CR DLTS technique are that the surface mobility of the MOS transistors does not need to be high, and that it is theoretically independent of the gate area of the transistor. This is expected, since the small amount of charge trapped beneath the gate must be balanced by a correction voltage applied across a relatively small gate–substrate capacitance.

Figure 20.40a shows six DLTS spectra for a junction field-effect transistor (JFET ) damaged with \({\mathrm{2.7\times 10^{9}}}\,{\mathrm{protons/cm^{2}}}\) [20.79, 20.81] with six selected rate windows. Using the temperatures at which the peaks occur and the rate windows, Arrhenius plots can be constructed as shown in Fig. 20.40b, where the energies of five electron trap levels below the conduction band are also indicated. For the five traps, the extracted capture cross sections were \({\mathrm{4.6\times 10^{-15}}}\,{\mathrm{cm^{2}}}\) (E1), \({\mathrm{6.3\times 10^{-15}}}\,{\mathrm{cm^{2}}}\) (E2), \({\mathrm{1.2\times 10^{-16}}}\,{\mathrm{cm^{2}}}\) (E3), \({\mathrm{8.5\times 10^{-16}}}\,{\mathrm{cm^{2}}}\) (E4) and \({\mathrm{3.4\times 10^{-15}}}\,{\mathrm{cm^{2}}}\) (E5).

## Notes

### Acknowledgements

The authors are very grateful to Drs. O. Marinov and D. Landheer for their careful review of the manuscript and their assistance. They are also grateful to several previous students and researchers whose collaborative research is discussed here. Finally, they are grateful to NSERC of Canada, the Canada Research Chair program and the CNRS of France for supporting this research.

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