Abstract
In this chapter, we focus on the Multiple-Times Programmable (MTP) embedded NVM using basic logic CMOS processes. Several types of floating-gate-based NVMs are discussed, including medium density eNVM based on two-transistor (2T) memory cell, and low density but also low-power three-transistor (3T) memory cell. In the last section, we review the charge trapping-based NVM cell design.
This is a preview of subscription content, log in via an institution.
Buying options
Tax calculation will be finalised at checkout
Purchases are for personal use only
Learn about institutional subscriptionsReferences
Diorio, C., Bernard, F., Humes, T., & Pesavento, A. (2007). Rewritable electronic fuses. US Patent 7,242,614.
Glidden, R., Bockorick, C., Cooper, S., Diorio, C., Dressler, D., Gutnik, V., et al. (2004). Design of ultra-low-cost UHF RFID tags for supply chain applications. IEEE Communications Magazine, 42(8), 140–151.
Lindhorst, C. A., Diorio, C. J., Gilliland, T. N., Pesavento, A., Srinivas, S., Ma, Y., et al. (2005). Differential floating gate nonvolatile memories. US Patent 6,950,342.
Ma, Y., Deng, R., Nguyen, H., Wang, B., Pesavento, A., Niset, M., et al. (2008). Floating-gate nonvolatile memory with ultrathin 5-nm tunnel oxide. IEEE Transactions on Electron Devices, 55, 3476–3481.
Ma, Y., Gilliland, T., Wang, B., Paulsen, R. P., Wang, C., Nguyen, H., et al. (2004). Reliability of pFET EEPROM with 70A tunnel oxide manufactured in generic logic CMOS processes. IEEE Transactions on Device and Materials Reliability, 4, 353–356.
Pesavento, A., Gilliand, T., Lindhorst, C., Srinivas, S., Bernard, F., Salazar, S., et al. (2004). Embedded non-volatile memory in logic CMOS. In Non-volatile Semiconductor Memory Workshop (p. 49). Monterey: IEEE.
Pesavento, A., & Hyde, J. (2013). PFET nonvolatile memory. US Patent 8,416,630.
Pevavento, A., & Langlinais, J. (2010). Radio frequency tag including configurable single-bit/dual-bits memory. US PTO. US Patent 7,796,450.
Runnion, E., Gladstone, S., Scott, R., Dumin, D. J., & Lie L. (1996). Limitation on oxide thicknesses in flash EEPROM applications. In Proceedings of International Reliability Physics Symposium (pp. 93–99). IEEE.
Sharma, U. (1993). A novel technology for megabit density, low power, high speed NVRAMs. In VLSI Symposium (p. 53). Japan.
Sung, Y., Lin, P., Chen, J., Chang, T., King, Y., & Lin, C. (2014). A new SAW-like self-recover of interface states in nitride-based memory cell. In Technical Digest of IEEE International Electron Device Meeting (pp. 494–497). San Francisco: IEEE.
Author information
Authors and Affiliations
Rights and permissions
Copyright information
© 2017 Springer International Publishing AG
About this chapter
Cite this chapter
Ma, Y., Kan, E. (2017). Multiple-Times Programmable Logic Nonvolatile Memory. In: Non-logic Devices in Logic Processes. Springer, Cham. https://doi.org/10.1007/978-3-319-48339-9_10
Download citation
DOI: https://doi.org/10.1007/978-3-319-48339-9_10
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-319-48337-5
Online ISBN: 978-3-319-48339-9
eBook Packages: EngineeringEngineering (R0)