Skip to main content

Physics and Technology of Emerging Non-Volatile Memories

  • Chapter
  • First Online:
Book cover In Search of the Next Memory

Abstract

Although flash technology has clearly demonstrated its capability to shrink the cell size according to Moore’s law, further reduction of the dimension is facing fundamental physical limits, and it is demanding technological developments that are making the cell scaling less convenient from the economic standpoint. To improve the performance and scalability with respect to floating-gate devices, innovative concepts for alternative NVM have been proposed in the past and are under investigation today, as we dream of find the ideal memory that combines fast read, fast write, non-volatility, low-power, and unlimited endurance, and obviously at a cost comparable to flash or DRAM.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 79.99
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 99.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 139.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

References

  1. R. Bez et al., “Introduction to Flash Memory”, Proceedings of the IEEE, vol. 91, n. 4, 2003.

    Google Scholar 

  2. “Flash Memories”, edited by P. Cappelletti, C. Golla, P. Olivo, E. Zanoni, Kluwer Academic Publishers, 1999.

    Google Scholar 

  3. G. Ginami et al., “Survey on Flash Technology with Specific Attention to the Critical Process Parameters Related to Manufacturing”, Proceedings of the IEEE, vol. 91, n. 4, p. 503, 2003.

    Google Scholar 

  4. A. Fazio, “A High Density High Performance 180 nm Generation ETOX Flash memory Technology”, IEEE IEDM Tech. Dig. pp. 267–270, 1999.

    Google Scholar 

  5. S. Keeney, “A 130 nm Generation High Density ETOX Flash Memory Technology”, IEEE IEDM Tech. Dig. pp. 2.5.1–2.5.4, 2001.

    Google Scholar 

  6. G. Servalli et al., “A 65 nm NOR Flash Technology with 0.042 μm2 Cell Size for High Performance Multilevel Application”, IEEE IEDM Tech. Dig., pp. 2.5.1–2.5.4, 2005.

    Google Scholar 

  7. H. Hu et al., “K = 0.266 immersion lithography patterning and its challenge for NAND FLASH”, Semiconductor Technology International Conference (CSTIC), 2015 China.

    Google Scholar 

  8. K. Naruke et al., “Stress Induced Leakage Current Limiting to Scale Down EEPROM Tunnel Oxide Thickness”, IEEE IEDM Tec. Dig., pp. 424–427, 1988.

    Google Scholar 

  9. J. S. Witters et al., “Degradation of Tunnel Oxide Floating Gate EEPROM Devices and Correlation with High Field Current Induced Degradation of Thin Gate Oxide”, IEEE Trans. Electron Devices, vol. 36, p. 1663–1682, 1989.

    Google Scholar 

  10. D. Ielmini et al., “A Statistical Model for SILC in Flash Memories”, IEEE Trans. Electron Devices, vol. 49, n. 11, p. 1955–1961, 2002.

    Google Scholar 

  11. Micron Press Release, “Intel, Micron Extend NAND Flash Technology Leadership With Introduction of World’s First 128 Gb NAND Device and Mass Production of 64 Gb 20 nm NAND”, December 6, 2011.

    Google Scholar 

  12. R. Micheloni et al., “Error Correction Codes for Non-Volatile Memories”, Springer-Verlag, 2008.

    Google Scholar 

  13. R. Micheloni et al., “A 4 Gb 2b/cell NAND Flash Memory with Embedded 5b BCH ECC for 36 MB/s System Read Throughput”, IEEE International Solid-State Circuits Conference Dig. Tech. Papers, pp. 142–143, Feb. 2006.

    Google Scholar 

  14. B. DeSalvo et al., “How Far Will Silicon Nanocrystals Push the Scaling Limits of NVMs Technologies?” IEEE IEDM Tech. Dig., p. 597–600, 2003.

    Google Scholar 

  15. Y. Shin et al., “A Novel NAND-type MONOS Memory using 63 nm Process Technology for Multi-Gigabit Flash EEPROMs”, IEEE IEDM Tech. Dig., p. 327–330, 2005.

    Google Scholar 

  16. B. Eitan et al. “NROM: A Novel Localized Trapping, 2-bit Nonvolatile Memory Cell”, IEEE EDL, Vol. 21, No. 11, 2000.

    Google Scholar 

  17. C. H. Lee et al., “A novel SONOS structure of SiO2/SiN/Al2O3 with TaN metal gate for multi-Giga bit Flash memories”, IEDM tech. digest 2003.

    Google Scholar 

  18. J. Kim et al., “Novel Vertical-Stacked-Array-Transistor (VSAT) for ultra-high-density and cost-effective NAND Flash memory devices and SSD (Solid State Drive)”, Symposium on VLSI technology 2009.

    Google Scholar 

  19. Micron Press Release, “Micron and Intel Unveil New 3D NAND Flash Memory”, March 26, 2015.

    Google Scholar 

  20. H. Tanaka et al., “Bit Cost Scalable technology with punch and plug process for ultra-high density Flash memory“, Symposium on VLSI technology 2007.

    Google Scholar 

  21. J. Kim et al., “Novel 3-D structure for ultra-high density Flash memory with VRAT (Vertical-Recess-Array-Transistor) and PIPE (Planarized Integration on the same Plane)”, Symposium on VLSI technology 2008.

    Google Scholar 

  22. J. Jang et al., “Vertical cell array using TCAT (Terabit Cell Array Transistor) technology for ultra-high density NAND Flash memory”, Symposium on VLSI technology 2009.

    Google Scholar 

  23. P. Vettiger et al., “The “Millipede”-More than thousand tips for future AFM storage”, IBM Journal of Research and Development, vol. 44, n. 3, pp. 323–340, 2000.

    Google Scholar 

  24. S.-H. Oh et al., “Novel FERAM Technologies with MTP Cell Structure and BLT Ferroelectric Capacitors”, IEEE IEDM Tech. Dig., p. 835–839, 2003.

    Google Scholar 

  25. H. Ishiwara, “Recent Progress in FET-Type Ferroelectric Memories”, IEEE IEDM Tech. Dig., p. 263–267, 2003.

    Google Scholar 

  26. M. Durlam et al., “A 0.18 um 4 Mb Toggling MRAM”, IEEE IEDM Tech. Dig., p. 995–999, 2003.

    Google Scholar 

  27. S. Tehrani et al., “Magnetoresistive Random Access Memory Using Magnetic Tunnel Junctions”, Proceedings of the IEEE, vol. 91, n. 5, p. 703–714, 2003.

    Google Scholar 

  28. J. C. Slonczewski, “Current-Driven Excitation of Magnetic Multilayers”, Journal of Magnetism and Magnetic Materials, vol. 159, n. 1–2, p. L1–L7, 1996.

    Google Scholar 

  29. C. Demerjian, “Everspin Makes ST-MRAM a Reality”, “LSI AIS 2012: Non-volatile Memory with DDR3 Speeds”, SemiAccurate.com, November 16, 2012.

    Google Scholar 

  30. S. Chung et al., “Fully Integrated 54 nm STT-RAM with the Smallest Bit Cell Dimension for High Density Memory Application”, IEEE IEDM Tech. Dig., p. 12.7.1–12.7.4, 2010.

    Google Scholar 

  31. S. R. Ovshinsky, “Reversible Electrical Switching Phenomena in Disordered Structures”, Phys. Rev. Lett., vol. 21, p. 1450, 1968.

    Google Scholar 

  32. R. G. Neale et al., “Nonvolatile and Reprogrammable, the Read-Mostly Memory is Here”, Electronics, p. 56, Sept., 1970.

    Google Scholar 

  33. G. Wicker, “Nonvolatile, High Density, High Performance Phase Change Memory” SPIE Conf. on Elect. and Struc. for MEMS, Australia, 1999.

    Google Scholar 

  34. F. Pellizzer et al., “Novel μTrench Phase-Change Memory Cell for Embedded and Stand-Alone Non-Volatile Memory Applications”, Symp. on VLSI Tech., p. 18–19, 2004.

    Google Scholar 

  35. F. Ottogalli et al., “Phase-Change Memory Technology for Embedded Applications”, Proc. ESSDERC 04, p. 293–296, 2004.

    Google Scholar 

  36. F. Bedeschi et al., “A Multi-Level-Cell Bipolar-Selected Phase-Change Memory”, Solid-State Circuits Conference, ISSCC, p. 428, 2008.

    Google Scholar 

  37. G. Servalli, “A 45 nm generation Phase Change Memory technology”, IEEE IEDM Tech. Dig., p. 1–4, 2009.

    Google Scholar 

  38. Micron Press Release, “Micron Announces Availability of Phase Change Memory for Mobile Devices”, July 18, 2012.

    Google Scholar 

  39. C. Villa, D. Mills, G. Barkley, H. Giduturi, S. Schippers, D. Vimercati, “A 45 nm 1 Gb 1.8 V Phase-Change Memory”, Solid-State Circuits Conference, ISSCC, p. 270–271, 2010.

    Google Scholar 

  40. R. F. Freitas and W. W. Wilcke, “Storage-Class Memory: The next Storage System Technology”, IBM Journal of Research and Development, vol. 52(4/5), p. 439–448, 2008.

    Google Scholar 

  41. T. Shintami et al., “Properties of Low-Power Phase-Change Device with GeTe/Sb2Te3 Superlattice Material”, EPCOS 2011, p. 110, 2011.

    Google Scholar 

  42. K. Szot et al., “Localized Metallic Conductivity and Self-Healing during Thermal Reduction of SrTiO3”, Phys. Rev. Lett., vol. 88, n. 7, p. 075508, 2002.

    Google Scholar 

  43. T. Iizuka-Sakano et al., “Stability of the Staging Structure of Charge-Transfer Complexes Showing a Neutral–Ionic Transition”, Phys. Rev. B, vol. 70, n. 8, p. 085111, 2004.

    Google Scholar 

  44. B. J. Choi et al., “Resistive Switching Mechanism of TiO2 Thin Films Grown by Atomic-Layer Deposition”, J. Appl. Phys., vol. 98, n. 3, p. 33715, 2005.

    Google Scholar 

  45. M. N. Kozicki et al., “Nonvolatile Memory Based on Solid Electrolytes”, NVMTS 2004.

    Google Scholar 

  46. Panasonic Press Release, “The New Microcontrollers with On-Chip Non-Volatile Memory ReRAM”, May 15, 2012.

    Google Scholar 

  47. T.-Y. Liu et al., “A 130.7mm2 2-Layer 32 Gb ReRAM Memory Device in 24 nm Technology”, Solid-State Circuits Conference, ISSCC, pp. 210, 2012.

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Agostino Pirovano .

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2017 Springer International Publishing AG

About this chapter

Cite this chapter

Pirovano, A. (2017). Physics and Technology of Emerging Non-Volatile Memories. In: Gastaldi, R., Campardo, G. (eds) In Search of the Next Memory. Springer, Cham. https://doi.org/10.1007/978-3-319-47724-4_3

Download citation

  • DOI: https://doi.org/10.1007/978-3-319-47724-4_3

  • Published:

  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-47722-0

  • Online ISBN: 978-3-319-47724-4

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics