Abstract
With shrinking feature sizes and increased chip sizes, the average delay of a logic gate is now dominated by the interconnection (metal wires) rather than by the transistor itself. Most of the potential electrical problems, such as cross-talk, critical timing, substrate bounce and clock skew, etc. are related to the signal propagation and/or high (peak) currents through these metal wires.
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Veendrick, H.J.M. (2017). Robustness of Nanometer CMOS Designs: Signal Integrity, Variability and Reliability. In: Nanometer CMOS ICs. Springer, Cham. https://doi.org/10.1007/978-3-319-47597-4_9
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DOI: https://doi.org/10.1007/978-3-319-47597-4_9
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