Abstract
With the predicted device, core, and multi-core scaling, a recent study revealed that regardless of chip organization and topology, multi-core scaling is power limited. It has been predicted that at 22 nm, 21 % of a fixed-size chip must be powered off, and at 8 nm, even more than 50 % (Esmaeilzadeh et al., News 39(3):365–376, 2011). Especially for mixed-criticality systems, which consist of a mixture of safety and non-safety relevant applications, this is of major concern. Safety-critical applications cannot be simply switched on and off or migrated during run-time. A system engineer should be aware of any possible cross-application interferences with respect to timing, power, and thermal properties as soon as possible in the design process. Introduction of power and temperature management must be planned and realized without violating freedom from interference. For this reason, the extra-functional properties need to be modeled and analyzed at the system level, because they can strongly affect the overall quality of service (performance, battery lifetime) or even cause the system to fail meeting its real-time and safety requirements.In this chapter, we present our vision of a SystemC-based simulation framework for capturing extra-functional properties in virtual platforms, currently under development in the CONTREX project. This covers the specification of platform properties (extra-functional model) as well as the dynamic capturing, processing, and extraction of power/temperature information during the simulation. Especially closing the loop back to the application and run-time services is an important feature for complex heterogeneous hardware platforms and software stacks. As an example, we will present a battery-powered mixed-critical avionics system, running a safety-critical flight control application and a performance critical image processing application on the same multi-core System on Chip.
With the support of many others, see Acknowledgments.
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Notes
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Running on the host computer.
- 2.
While the MicroBlaze timing model is close to clock cycle accuracy, the ARM timing model is working on a coarse-grained instructions per cycle level.
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Acknowledgements
Many thanks to the CONTREX team members Ralph Görgen, Sven Rosinger, Sören Schreiner, Marco Feltes, and Martin Bornhold, my colleagues Henning Schlender and Malte Metzdorf, and the master students Jörn Bellersen, Martin Bornhold, Marco Braun, Henning Elbers, Thomas Nordlohne, Niklas May-Johann, Jenny Röbesaat, André Schaadt, Patrick Schmale, Steven Schmidt, Sebastian Vander Maelen, and Markus Wieghaus for their great work and enthusiasm on the multi-rotor use-case.
This work has been partially supported by the EU integrated project CONTREX (FP7-611146) and the ARTEMIS project EMC2 (01-IS14002R) partially funded by the EC and the German Federal Ministry of Education and Research (BMBF).
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Grüttner, K. (2017). Empowering Mixed-Criticality System Engineers in the Dark Silicon Era: Towards Power and Temperature Analysis of Heterogeneous MPSoCs at System Level. In: Molnos, A., Fabre, C. (eds) Model-Implementation Fidelity in Cyber Physical System Design. Springer, Cham. https://doi.org/10.1007/978-3-319-47307-9_3
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