Optimization of Read-Only Memory Program Models Mapping into the FPGA Architecture

Conference paper
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 522)

Abstract

The problem of mapping the read-only memory program models, being the components of the application-specific processors, into the programmable logical integral circuit architecture will be considered. The existing approaches to the data compression in the read-only memory devices are analyzed and, alternatively, a new approach is suggested allowing a high degree of compression to be achieved and the FPGA resources to be used more rationally.

Keywords

FPGA Application-specific processors program models Read-only memory Data compression 

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Copyright information

© Springer International Publishing AG 2017

Authors and Affiliations

  1. 1.The John Paul II Catholic University of LublinLublinPoland
  2. 2.Lviv Polytechnic National UniversityLvivUkraine

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