Abstract
The problem of mapping the read-only memory program models, being the components of the application-specific processors, into the programmable logical integral circuit architecture will be considered. The existing approaches to the data compression in the read-only memory devices are analyzed and, alternatively, a new approach is suggested allowing a high degree of compression to be achieved and the FPGA resources to be used more rationally.
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Melnyk, V., Lopit, I. (2017). Optimization of Read-Only Memory Program Models Mapping into the FPGA Architecture. In: Grzech, A., Świątek, J., Wilimowska, Z., Borzemski, L. (eds) Information Systems Architecture and Technology: Proceedings of 37th International Conference on Information Systems Architecture and Technology – ISAT 2016 – Part II. Advances in Intelligent Systems and Computing, vol 522. Springer, Cham. https://doi.org/10.1007/978-3-319-46586-9_3
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DOI: https://doi.org/10.1007/978-3-319-46586-9_3
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Online ISBN: 978-3-319-46586-9
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